VC Verification IP for MIPI I3C
Synopsys® VC Verification IP for MIPI I3C provides a comprehensive set of protocol, methodology, verification and ease-of-use features, enabling users to achieve accelerated verification closure of MIPI I3C designs.
Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
- I3C v1.0 specifications supported
- All topologies Single Master-Single Slave (I3C/I2C)
- Single Master-Multi Slave
- Multi Master-Single Slave
- Multi Master-Multi Slave
- Legacy I2C Slave agent can be configured as a generic slave or as an EEPROM slave
- Dynamic Address allocation
- Common Command Codes
- Transactions as per SDR frame format
- Hot-Join feature
- Interrupt request handling
- High Data Rate—TSP (Ternary symbol pure bus), TSL (Ternary symbol legacy inclusive bus), DDR (Double data rate)