VC Verification IP for MIPI RFFE

Synopsys VC Verification IP for MIPI RFFE provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MIPI RFFE based designs.

VC VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.. 

Verification IP for MIPI RFFE


  • Native SystemVerilog/UVM
  • Source code test suite (Optional)
  • Runs on all major simulators
  • Verification plan and coverage
  • Built-in protocol checks
  • Error injection and exceptions

Key Features

  • MIPI RFFE 3.0(EA), 2.1, 2.0
  • Single/dual bus topology - multiple masters and slaves
  • CLK frequency rates - standard/extended mode
  • All command sequences
  • Primary/secondary mode support
  • Trigger mode
  • Interrupt capable slaves
  • Delayed read-back
  • Configurable IPG (Inter Packet Gap)
  • Master ownership handover
  • Synchronous reads (sREAD)
  • Half speed data response (HSDR)
  • Identification features
  • USID programming
  • Broadcast writes
  • Lower than half speed raes
  • Manufacturer ID extension
  • Silent BPC
  • Bus clocked condition
  • Extended trigger Block B
  • Timed and mappable triggers