VC Verification IP for MIPI RFFE

Synopsys® VC Verification IP for MIPI RFFE provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MIPI RFFE based designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native SystemVerilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage. 

MIPI RFFE VC Verification IP

Protocol Features

  • MIPI RFFE v2.0 specification
  • Single/dual Bus topology — multiple masters and slaves
  • CLK Frequency Rates — Standard/Extended Mode
  • All command sequences
  • Primary / Secondary mode support
  • Trigger Mode
  • Interrupt Capable Slaves
  • Delayed Readback
  • Configurable IPG (Inter Packet Gap)
  • Master Ownership Handover
  • Synchronous Reads (sREAD)
  • Half Speed Data Response (HSDR)
  • Identification Features
  • USID Programming
  • Broadcast Writes