VC Verification IP for MIPI DSI

Synopsys VC Verification IP for MIPI Display Serial Interface (DSI) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of DSI Hosts and Devices. MIPI-DSI VIP supports both High Speed (HS) transmission and Escape Mode. In Escape Mode it supports Ultra Low Power State (ULPS), Low Power Data Transmission (LPDT), Trigger messages and Bus Turnaround. It simplifies testbench development by enabling engineers to use a single VIP to verify multiple transmission modes across the full DSI protocol.

Verification IP for MIPI DSI

Protocol Features

  • Supports DSI standard with specification revision 1.2.r06 04 March 2014 
    Compliant with D-PHY specification revision 1.1 
  • Protocol Layer
    • DSI Host, DSI Device
    • Four virtual channels
    • DCS command, generic commands and Video Mode
    • Short and Long Packet structures
    • Multiple High Speed (HS) packets per transmission
    • Video transmission in burst and non-burst modes
    • 16BPP, 18BPP and 24BPP, 30 BPP, 36 BPP RGB pixel formats in video mode
    • Normal as well as interleaved data streams, ECC generation, Checksum (CRC) generation and checking
    • Error Detection and Reporting
    • Dual DSI
    • DSC Compression and Decompression
  • Physical Layer
    • D-PHY Serial and Parallel (PPI) Interface
    • One to four PHY data lanes and one clock lane