VC Verification IP for MIPI DSI

Synopsys VC Verification IP for MIPI Display Serial Interface (DSI) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of DSI Host and Device. MIPI DSI VIP supports both High Speed (HS) transmission and Escape Mode. In Escape Mode it supports Ultra Low Power State (ULPS), Low Power Data Transmission (LPDT), Trigger messages and Bus Turnaround. It simplifies testbench development by enabling engineers to use a single VIP to verify multiple transmission modes across the full DSI protocol.

Verification IP for MIPI DSI

Highlights

  • Native SystemVerilog/UVM, Verilog
  • Source code test suite (optional)
  • Runs on all major simulators
  • Built-in protocol checks
  • Verification plan and coverage
  • Verdi protocol analyzer
  • Error injection and exceptions

Key Features

  • DSI-2 v1.0 with D-PHY v2.0 and C-PHY v1.2/1.1/1.0
  • DSI v1.3/1.2/1.1 with D-PHY v1.2/1.1
  • Host and Device
  • Dual DSI
  • DSC compression/decompression
  • Four virtual channels
  • DCS and generic commands, video mode
  • Short and long packet structures
  • Multiple high speed (HS) packets per transmission
  • Video transmission in burst and non-burst modes
  • 16/18/24/30/36 BPP RGB pixel formats in video mode
  • Normal and interleaved data streams
  • ECC and checksum (CRC) generation and checking
  • D-PHY/CPHY serial and parallel (PPI) Interface
  • D-PHY: 1-4 PHY data and 1 clock lane
  • C-PHY: 1-4 PHY lanes
  • High Speed, Escape Mode Transmission
  • Global operational timing parameters