Highlights
- SystemVerilog testbench
- Native UVM support
- Runs natively on VCS and VCSMX
- Protocol-aware debug
- Built-in verification plan and coverage
- Built-in Protocol checks
- HTML based documentation
- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers
< Silicon Design & Verification
Silicon Design & Verification
< Products
< Products
< Products
< Products
< Products
< Products
< Products
Photonic Solutions
PIC Design Suite
< Silicon Design & Verification
< Solutions
< Solutions
< Solutions
Cloud
Synopsys on the Cloud
< Solutions
< Silicon Design & Verification
< Resources
< Resources
Verification
Articles
Blogs
Datasheets
Events
News
Newsletters
Success Stories
Videos
Webinars
White Papers
< Resources
< Silicon Design & Verification
< Services
< Services
< Services
< Silicon Design & Verification
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Silicon Design & Verification
< Training
< Silicon Design & Verification
Training
Training and Education
< main menu
< Silicon IP
Silicon IP
< Products
< Products
Processor Solutions
ARC Processor IP
Embedded Vision Processor IP
Development Tools
Operating Systems
Ecosystem
ASIP Tools
< Products
Memories & Libraries
Logic Libraries
Memory Compliers
Duet Packages
HPC Design Kit
Embedded Test & Repair
Non-Volatile Memory
< Products
< Products
Analog IP
Data Converters
< Products
< Products
< Products
< Silicon IP
< Markets
< Silicon IP
Newsletter
< Silicon IP
Customer Success
< Silicon IP
News
< Resources
< Resources
< main menu
< Software Integrity
Polaris Platform
Comprehensive application security from developer to deployment
< Software Integrity
< Software Integrity
< Software Integrity
Professional Services
Strategy and programs that address security before, during and after development
< Software Integrity
< Tools
< Tools
< Tools
< Tools
< Software Integrity
< Services
Managed Security Testing
Managed SAST
Dynamic Analysis (DAST)
Penetration Testing
Mobile Application Security Testing
Network Security Testing
< Services
Professional Services
Strategy and Planning (BSIMM)
Architecture & Design
DevSecOps Integration
Cloud Security
Industry Solutions
< Services
< Software Integrity
< Training
< Training
Product Education
< Training
Community
< Software Integrity
< Solutions
< Solutions
< Resources
< Resources
< Software Integrity
< Software Integrity
Customers
< Partners
< Partners
Become a partner
< Software Integrity
< Software Integrity
Blog
< main menu
< About Us
Company
< About Us
< About Us
About Us
About Us
< Investor Relations
< About Us
Investor Relations
Investor Relations
< Community
< About Us
Community
Community
< Newsroom
< About Us
Newsroom
Newsroom
< Resources
< About Us
Resources
Resources
< Careers
< About Us
Careers
Careers
< main menu
VC Verification IP for MIPI DigRFv4
Synopsys VC Verification IP for MIPI DigRF provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of the interface between a Baseband IC (BBIC) and a Radio Frequency IC (RFIC) in a mobile terminal. It provides support for high speed and low speed operations with multiple standby modes and simplifies testbench development by enabling engineers to use a single VIP to verify multiple speeds across the full DigRF protocol.
Protocol Features
Protocol Layer
- Configurable low speed (LS) mode, high speed (HS1P, HS2P, HS1S, HS2S) modes, and multiple standby modes (SLEEP, STALL, HIBERNATE)
- Configurable 1/2/3/4 Tx Lane(s), and 1/2/3/4 Rx Lane(s) per sub-link
- Support for data/control logic channels, ICLC messages, nested frames, dummy frames, IDLE symbols, marker symbols (SOF, EOF and EOT)
- Link test modes: Ping Message and Clock Test mode
- Programmable parameters like PREPARE length, SYNC pattern length
- CRC generation, Error Detection and Retransmission (ARQ scheme: NACK)
Physical Layer
- M-PHY Serial and Parallel (RMMI) Interface
- Serializer (M-TX) or Deserializer (M-RX), 8B10B coding (M-TX) or 8B10B decoding (M-RX)
- Support for capability, status and configuration attributes