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VC Verification IP for MIPI DigRFv4
Synopsys VC Verification IP for MIPI DigRF provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of the interface between a Baseband IC (BBIC) and a Radio Frequency IC (RFIC) in a mobile terminal. It provides support for high speed and low speed operations with multiple standby modes and simplifies testbench development by enabling engineers to use a single VIP to verify multiple speeds across the full DigRF protocol.
Highlights
- SystemVerilog testbench
- Native UVM support
- Runs natively on VCS and VCSMX
- Protocol-aware debug
- Built-in verification plan and coverage
- Built-in Protocol checks
- HTML based documentation
Protocol Features
Protocol Layer
- Configurable low speed (LS) mode, high speed (HS1P, HS2P, HS1S, HS2S) modes, and multiple standby modes (SLEEP, STALL, HIBERNATE)
- Configurable 1/2/3/4 Tx Lane(s), and 1/2/3/4 Rx Lane(s) per sub-link
- Support for data/control logic channels, ICLC messages, nested frames, placeholder frames, IDLE symbols, marker symbols (SOF, EOF and EOT)
- Link test modes: Ping Message and Clock Test mode
- Programmable parameters like PREPARE length, SYNC pattern length
- CRC generation, Error Detection and Retransmission (ARQ scheme: NACK)
Physical Layer
- M-PHY Serial and Parallel (RMMI) Interface
- Serializer (M-TX) or Deserializer (M-RX), 8B10B coding (M-TX) or 8B10B decoding (M-RX)
- Support for capability, status and configuration attributes