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VC Verification IP for MIPI CSI-2
Synopsys VC Verification IP for MIPI CSI-2 (Camera Serial Interface) provides a comprehensive set of protocol, methodology, verification and productivity features enabling users to achieve rapid verification of MIPI CSI TX and RX devices. It also includes VIP for MIPI D-PHY and C-PHY for physical layer verification. CSI-2 supports data-type interleaving frames, normal frames and Virtual Channel ID interleaving frames. It simplifies testbench development by enabling engineers to use a single VIP to verify multiple transmission modes across the full CSI-2 protocol.
Highlights
- Native SystemVerilog/UVM and Verilog
- Source code test suite (optional)
- Runs natively on all major simulators
- Built-in Protocol checks
- Verification plan and coverage
- Verdi® protocol analyzer
- Error injection and exceptions
Key Features
- CSI-2 3.0 (EA)
- CSI-2 up to 2.1 with C-PHY up to 1.2 and D-PHY up to 2.1
- 16/32 virtual channels for D-PHY/C-PHY
- Transmitter and Receiver
- Data scrambling
- All types of short and long packets
- Interleaved and normal frames
- Unidirectional data transfer
- ECC, Checksum (CRC) generation and checking
- Inoperative/operative mode of frame and line number
- D-PHY/C-PHY: Serial and PHY Protocol Interface (PPI)
- D-PHY: 1-16 PHY data lanes and 1 clock lane
- C-PHY: 1-4 PHY lanes
- High Speed and Escape Mode Transmission
- Global operational timing parameters
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