Architecture and Key Features

Specifications

  • CSI-2 4.0, 3.0, 2.1
  • C-PHY 2.1, 2.0
  • D-PHY 3.0, 2.5

DUT Types/Topology: Tx and Rx

Key VIP Features

  • API based transaction flow for ease of use
  • Specification linked Functional coverages
  • Scoreboard, callbacks and error injection

Debug and Analysis

  • Verdi based protocol and performance analysis
  • Protocol checks at each layer
  • Debug ports, transaction logs, and trace files

 

Key Protocol Features

  • Physical Layer
    • Configurable to C-PHY/D-PHY, Serial and Parallel (PPI) interface
    • High Speed and Escape Mode
    • Multi-Lane support (1 to N)
    • Configurable global timing parameters
    • Run-time reconfiguration of dynamic parameters
    • Lane transaction error injection
  • Protocol Layer
    • 4, 16, 32 virtual channels (CSI-2 1.x, CSI-2 2.0 with C/D-PHY )
    • All type of packets (Short/Long,RAW28 for CSI2 v4.0 RAW24 for CSI2v3.0)
    • Interleaved and normal frames, Operative/Inoperative line and frame number
    • ECC, CRC generation and checking
    • Error detection and recording, Data Scrambling and Compression for RAW Data Type Support
    • LRTE with D-PHY and C-PHY, USL Support for CSI2 v3.0

Test Suites / Groups Features

  • Tests targeting Protocol layer, Physical layer, CCI Interface, Error Injection Scenarios
Verification IP for MIPI CSI-2

VIP Architecture

ASK SYNOPSYS
BETA
Ask Synopsys BETA This experience is in beta mode. Please double check responses for accuracy.

End Chat

Closing this window clears your chat history and ends your session. Are you sure you want to end this chat?