Highlights
- Native SystemVerilog/UVM and Verilog
- Source code test suite (optional)
- Runs natively on all major simulators
- Built-in Protocol checks
- Verification plan and coverage
- Verdi® protocol analyzer
- Error injection and exceptions
- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Software Integrity
- Tools & Services
- Solutions
- Training
- Customers
- Resources
- Partners
- Blog
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers
< Silicon Design & Verification
Silicon Design & Verification
< Products
< Products
< Products
< Products
< Products
< Products
< Products
< Silicon Design & Verification
< Solutions
< Solutions
Cloud
Synopsys in the Cloud
< Solutions
< Solutions
Optical Design Solutions
Lighting Simulation Software
Optical Design Software
Automotive Lighting Design Software
< Solutions
< Solutions
Photonic Solutions
RSoft Photonic Device Tools
Photonic System Tools
PIC Design Software
OptoCompiler
< Silicon Design & Verification
< Resources
< Resources
Verification
Articles
Blogs
Datasheets
Events
News
Newsletters
Success Stories
Videos
Webinars
White Papers
< Resources
< Silicon Design & Verification
< Services
< Services
< Services
< Silicon Design & Verification
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Silicon Design & Verification
< Training
< Silicon Design & Verification
Training
Training and Education
< main menu
< Silicon IP
Silicon IP
< Products
< Products
Processor Solutions
ARC Processor IP
Embedded Vision Processor IP
Development Tools
Operating Systems
Ecosystem
ASIP Tools
< Products
Memories & Libraries
Logic Libraries
Memory Compilers
Duet Packages
HPC Design Kit
Embedded Test & Repair
Non-Volatile Memory
< Products
< Products
Analog IP
Data Converters
< Products
< Products
< Products
< Silicon IP
< Markets
< Silicon IP
Newsletter
< Silicon IP
Customer Success
< Silicon IP
News
< Resources
< Resources
< main menu
< Software Integrity
Software Integrity
< Tools & Services
Platform
Polaris DevSecOps Platform
< Tools & Services
< Tools & Services
< Solutions
< Solutions
< Software Integrity
< Training
< Training
Product Education
< Training
Community
< Software Integrity
< Software Integrity
Customers
< Resources
< Resources
< Software Integrity
< Partners
< Partners
Become a partner
< Software Integrity
< Software Integrity
Blog
< main menu
< About Us
Company
< About Us
< About Us
About Us
About Us
< Investor Relations
< About Us
Investor Relations
Investor Relations
< Community
< About Us
Community
Community
< Newsroom
< About Us
Newsroom
Newsroom
< Resources
< About Us
Resources
Resources
< Careers
< About Us
Careers
Careers
< main menu
VC Verification IP for MIPI CSI-2
Synopsys VC Verification IP for MIPI CSI-2 (Camera Serial Interface) provides a comprehensive set of protocol, methodology, verification and productivity features enabling users to achieve rapid verification of MIPI CSI TX and RX devices. It also includes VIP for MIPI D-PHY and C-PHY for physical layer verification. CSI-2 supports data-type interleaving frames, normal frames and Virtual Channel ID interleaving frames. It simplifies testbench development by enabling engineers to use a single VIP to verify multiple transmission modes across the full CSI-2 protocol.
Key Features
- CSI-2 3.0 (EA)
- CSI-2 up to 2.1 with C-PHY up to 1.2 and D-PHY up to 2.1
- 16/32 virtual channels for D-PHY/C-PHY
- Transmitter and Receiver
- Data scrambling
- All types of short and long packets
- Interleaved and normal frames
- Unidirectional data transfer
- ECC, Checksum (CRC) generation and checking
- Inoperative/operative mode of frame and line number
- D-PHY/C-PHY: Serial and PHY Protocol Interface (PPI)
- D-PHY: 1-16 PHY data lanes and 1 clock lane
- C-PHY: 1-4 PHY lanes
- High Speed and Escape Mode Transmission
- Global operational timing parameters