VC Verification IP for MIPI SoundWire

Synopsys® VC Verification IP for MIPI SoundWire provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of MIPI SoundWire devices operating with Basic and High-PHY links. VC VIP MIPI SoundWire is integrated with Protocol Analyzer, a protocol centric debug environment that gives users an easy to understand, graphical view of complex and highly interleaved traffic. VC VIP MIPI SoundWire is written entirely in SystemVerilog to run natively in the simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and a sequence collection.

MIPI SoundWire VC Verification IP

Protocol Features

  • Supports MIPI Alliance SoundWire 1.0 specification
  • Interfaces
    • DDR/NRZI signaling
    • Multi-Lane support
    • Internal/external clocking
  • Synchronization and Enumeration
  • Normal and Flow Control payload transport
  • Bank switching
  • Resets and Interrupts
  • Test Data Modes and Clock Stop Mode
  • High-PHY
  • Dynamic number of Slaves
  • Protocol Checks
  • Error Injection
  • Extensive Callbacks and Messaging
  • Passive Monitor

Test Suites

The Test Suite for MIPI SoundWire is a complete self-contained, configurable environment targeted at the verification of MIPI SoundWire designs. It is provided as SystemVerilog UVM source code to simplify integration, enable user customization and maximize reuse across projects. The MIPI SoundWire test suite incorporates Synopsys’ technology leading native-SystemVerilog VC VIP for MIPI SoundWire.