Synopsys® VC Verification IP for MIPI SoundWire provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of MIPI SoundWire devices operating with basic and High-PHY links. VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with built-in verification plans, example tests, and functional coverage. VIP is natively integrated with Verdi® Protocol Analyzer, a protocol centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.
SoundWire Device Class for Audio Register Controls (SDCA)
Commit Mechanism for Dual Ranked Registers
Atomic Access Mechanism for Multi-byte Quantities
Bus Clock Speed Encoding
The Test Suite for MIPI SoundWire is a complete self-contained, configurable environment targeted at the verification of MIPI SoundWire designs. It is provided as SystemVerilog UVM source code to simplify integration, enable user customization and maximize reuse across projects. The MIPI SoundWire test suite incorporates Synopsys’ technology leading native SystemVerilog VC VIP for MIPI SoundWire.