VC Verification IP for MIPI SoundWire

Synopsys® VC Verification IP for MIPI SoundWire provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of MIPI SoundWire devices operating with basic and High-PHY links. VIP can be integrated, configured and customized with minial effort. Testbench development is accelerated with built-in verification plans, example tests, and functional coverage. VIP is natively integrated with Verdi Protocol Analyzer, a protocol centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.

Verification IP for MIPI SoundWire

Highlights

  • Native SystemVerilog/UVM
  • Optional source code Testsuite
  • Runs natively on all major simulators
  • Verification plan and coverage
  • Built-in protocol chevks
  • Verdi protocol-aware debug
  • Error injection

Key Features

  • MIPI Alliance SoundWire 1.0 specification
  • Interfaces
    • DDR/NRZI signaling
    • Multi-Lane support
    • Internal/external clocking
  • Synchronization and Enumeration
  • Normal and Flow Control payload transport
  • Bank switching
  • Resets and Interrupts
  • Test Data Modes and Clock Stop Mode
  • High-PHY
  • Dynamic number of Slaves
  • Bulk payload transport
  • Extensive callbacks and messaging
  • Configurable data ports

Test Suites

The Test Suite for MIPI SoundWire is a complete self-contained, configurable environment targeted at the verification of MIPI SoundWire designs. It is provided as SystemVerilog UVM source code to simplify integration, enable user customization and maximize reuse across projects. The MIPI SoundWire test suite incorporates Synopsys’ technology leading native-SystemVerilog VC VIP for MIPI SoundWire.