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VC Verification IP for MIPI M-PHY
Synopsys VC Verification IP for MIPI M-PHY provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of M-PHY links operating in high speed and low speed modes.
Protocol Features
- Supports MIPI ALLIANCE specification for M-PHY Version 3.0, 4.0 and 4.1, 5.0(EA)
- M-PHY Layer (L 1.0) Features
- Interfaces
- SERIAL SYS and PWM signaling
- RMMI – controller and PHY
- TYPE_I and TYPE_II MODULE
- HS and LS GEARS
- Interfaces
- M-PORT LM Layer (L1.5) Features
- Configurable number of lanes
- Supports asymmetrical lanes between Tx Sublink and Rx Sublink
- Lane alignment at symbol boundary
- Lane splitting and merging
- Configurable number of frames
- FILLER insertion
- Lane-to-Lane skew
- M-PORT LM layer system monitor
- Configure VIP as MPHY model
- Configurable number of lanes
- CTRL and DATA SAP interface
- Interface with protocol adaptor layer
- Independent port/channel for CTRL and DATA SAPs
- All capability and configuration attributes
- LS – HS mode change and HS –LS mode change
- Gear change
- External/internal SYNC support
- Automatic FILLER insertion
- Configurable timing attributes
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