Highlights
- Native SystemVerilog/UVM
- Optional source code Test Suites
- Runs natively on all major simulators
- Built-in protocol checks
- Built-in verification plan and coverage
- Extensive error injection
Synopsys® VC Verification IP for MIPI SLIMbus provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MIPI SLIMbus based designs. Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.