VC Verification IP for MIPI DBI-2

Synopsys VC Verification IP for MIPI Display Bus Interface (DBI 2) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of DBI Host and DBI Device. Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, offers native performance, ease of use and advanced debugging solutions. VC VIP can be integrated, configured and customized with minimal effort and time. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

Verification IP for MIPI DBI2


  • SystemVerilog testbench
  • Native UVM support
  • Runs natively on all major simulators
  • Verdi® integrated protocol aware debug GUI
  • Built-in Protocol checks
  • HTML based documentation

Protocol Features

Supports DBI2 specification version v2.0

  • DBI Host and DBI Device
  • Supports Type A, Type B, Type C Architecture
  • Supports 16-bit, 18bit data bus widths
  • Tearing effect is supported
  • SDA Enabling/Disabling through DBI configuration
  • Configurable DBI configuration parameters using DBI configuration
  • DSC command set