VC Verification IP for AMBA APB

Synopsys VC Verification IP for Arm® AMBA® APB™ provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA based designs supporting APB4/APB3/APB2.

Verification IP for AMBA APB

Highlights

  • Native SystemVerilog/Verilog with UVM
  • Includes Master, Slave, Monitor
  • Runs natively on all major simulators
  • Built-in UVM sequence library
  • Verdi protocol aware debug

Key Features

AXI Interconnect Test Suites Available

  • Support for APB4/APB3/APB2
  • APB2 Features
    • Master initiates transfers on the Peripheral Bus
    • Master supports Write, Read, and Idle transactions
    • Master supports maximum of 16 slave devices
    • Slave memory response modeled by sequences
  • APB3 features
    • Slave supports wait states using PREADY signal
    • Slave supports error response using PSLVERR signal
  • APB4 features
    • Master supports write strobe using PSTRB signal
    • Trace Data Transfer (Valid, ready signaling)