VC Verification IP for AMBA ATB

Synopsys VC Verification IP for Arm® AMBA® ATB™ provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA ATB based designs.

Verification IP for AMBA ATB

Highlights

  • Native SystemVerilog/Verilog with UVM
  • Includes Master, Slave, Monitor
  • Runs natively on all major simulators
  • Built-in UVM sequence library
  • Verdi protocol aware debug

Key Features

AXI Interconnect Test Suites Available

  • Trace Data Transfer (Valid, ready signaling) 
  • Narrow Trace Data Transfer (Data Valid Bytes signaling) 
  • Flow Control (Valid, ready signaling) 
  • Flush Request Response (Flush Valid, Ready signaling with Data transfer) 
  • Synchronization Request capture and pass to Trace Source (i.e. Sequence layer) 
  • Slave Random Response for Trace Data Transfer 
  • Slave Random Flush Request Generation 
  • Slave Random Synchronization Request Generation 
  • Slave Memory (for Trace Data capture)