Highlights
- Native SystemVerilog/Verilog with UVM
- Includes Master, Slave, Monitor
- Runs natively on all major simulators
- Built-in UVM sequence library
- Verdi® protocol aware debug
Synopsys VC Verification IP for Arm® AMBA® ATB™ provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA ATB based designs.
AXI Interconnect Test Suites Available