Mastering AI Chip Complexity
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Synopsys Verification IP (VIP) for Arm® AMBA® AXI4-Stream™ provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA-based designs supporting AXI4-Stream.
Highlights
- Native SystemVerilog/Verilog with UVM
- Runs natively on all major simulators
- Reference Verification Platform
- Built-in verification plan and coverage
- Verdi® protocol aware debug
- Debug port for transaction tracking on waveforms
Key Features
AXI Interconnect Test Suites Available
- Includes Master, Slave, Monitor
- Ability to control wait states and slave response types
- Ability to control signal values during idle periods