EDA
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Synopsys Verification IP (VIP) for Arm® AMBA® ACE provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA-based designs supporting AMBA ACE 5, H, J and K, ACE4, ACE-Lite, AXI5, AXI-J/K/L, AXI4, AXI4-Lite, and AXI3.
AMBA ACE Protocol Features
AXI Interconnect Test Suites Available
- Complete protocol support for AMBA ACE 5, H, J and K, ACE4, ACE-Lite, AXI5, AXI-J/K/L, AXI4, AXI4-Lite, and AXI3.
- Configurable interconnect model for AXI5, AXI4, AXI, ACE5, and ACE4
- Backdoor access to ACE primary cache
- Ability to control delays for valid and ready signals with respect to reference events
- Ability to control signal values during idle periods
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