Synopsys Verification IP (VIP) for Arm® AMBA® AXI™ provides a comprehensive set of protocol, methodology, verification and productivity features. Users are able to achieve rapid verification convergence on their AMBA AXI5, AXI-J/K/L, AXI4, AXI3, and AXI4-Lite based designs. 

Verification IP for AMBA AXI

AMBA AXI Protocol Features

  • Complete protocol support for AXI5, AXI-J/K/L, AXI4, AXI4-Lite, AXI3
  • Programmable number of Managers, Subordinates, and Port Monitors
  • Interconnect model
  • System Monitor
  • Port & System Level Sequencers
  • Sequence Library with port & System Level Sequences
  • Port level protocol checks for all interfaces
  • System-level checks for protocol and data integrity
  • Debug port for transaction tracking on waveforms
  • Built-in Functional Coverage Model
  • Protocol-aware debugging using Protocol Analyzer
  • Ability to control delays for valid and ready signals with respect to reference events
  • Ability to control signal values during idle periods
ASK SYNOPSYS
BETA
Ask Synopsys BETA This experience is in beta mode. Please double check responses for accuracy.

End Chat

Closing this window clears your chat history and ends your session. Are you sure you want to end this chat?