EDA
System
IP
SolvNetPlus
Training & Education
Architecture and Key Features
Specifications: AMBA CHI C2C Issue A and B
DUT Types/Topology: Interconnect, *PU, Memory Controller
Key VIP Features
- Key VIP Features
- Specification linked Functional coverages
- Built in Sequence Collection (RN, SN, System Level)
- System Verilog testbench
- Streaming protocol layer
- AXI Manager and Subordinate traffic use 4B or 64B data widths
- Built-in testbench Scoreboard
- Transaction ordering feature
- Data before address scenarios supported
- System Monitor
- System checks across interconnect ports (CHI, ACE, AXI)
- Correctness of sequencing/response between coherent and snooptransactions
- Data integrity between coherent transactions and snoop transactions
- Coherency between Manager caches
Debug and Analysis
- Verdi based protocol, performance analysis & Cache Visualization
- Protocol checks at each layer
- Debug ports and trace files and verbosity messages
- Protocol-aware transactions & attributes
Key Protocol Features
- Acts as application layer over separately procured Synopsys AMBA 5 CHI VIP
- Sync Ack Handshake
- Credit Flow control
- Port Aggregation with 64B and 4B ports
- Aligned/Unaligned addresses
Test Suites / Group Features: Provides specification mapped Verification Plans with functional coverage,protocol checks and test-cases
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