VC Verification IP for SMBUS

Synopsys® VC Verification IP for SMBUS provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of SMBUS designs.

Verification IP for SMBUS


  • Native SystemVerilog/UVM testbench
  • Runs natively on major simulators
  • Protocol checks
  • Verification plan and coverage
  • Error injection

Key Features

  • SMBus v3.0 specification
  • Standard-mode, fast-mode and fast-mode plus
  • 7-bit addressing mode
  • All commands supported (except host notify)
  • PEC Support
  • SMBALERT support
  • ARP Support
  • Multi primary secondary configuration