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VC Verification IP for SMBUS
Synopsys® VC Verification IP for SMBUS provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of SMBUS designs.
Highlights
- Native SystemVerilog/UVM testbench
- Runs natively on major simulators
- Protocol checks
- Verification plan and coverage
- Error injection
Key Features
- SMBus v3.0 specification
- Standard-mode, fast-mode and fast-mode plus
- 7-bit addressing mode
- All commands supported (except host notify)
- PEC Support
- SMBalert support
- ARP Support
- Multi master slave configuration