VC Verification IP for OCP

Synopsys VC Verification IP (VIP) for OCP provides a comprehensive set of protocol, methodology, verification and productivity features enabling users to achieve rapid verification of OCP 3.0, 2.2, 2.1 and 2.0 interfaces. VC VIP OCP acts as either a master or slave device and can be used to verify OCP based cores or interconnects.

Verification IP for OCP

Highlights

  • SystemVerilog and Verilog testbench
  • Native UVM and VMM support
  • Runs natively on VCS and other simulators
  • Protocol-aware debug
  • Built-in verification plan and coverage
  • Built-in protocol checks
  • HTML based documentation
  • Source code visibility

Key Features

  • Covers full range of OCP configurations
  • Multi-threading and bursts
  • Configurable as core or system
  • 2.1 tagging
  • 2.2 thread busy pipelined
  • 2.2 Errata
  • Connect/Disconnect
  • 2-dimensional block burst sequences
  • Non-blocking flow control
  • Cache coherence
  • Full built-in coverage of OCP-IP defined functional coverage groups