VC Verification IP for I2C

Synopsys VC Verification IP for I2C provides a comprehensive set of protocol, methodology, verification and ease-of-use features, enabling users to achieve accelerated verification closure of I2C designs. Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

Verification IP for I2C

Highlights

  • SystemVerilog and Verilog testbench
  • Native UVM and OVM support
  • Runs natively on all major simulators
  • Verdi Protocol-aware debug
  • Verification plan and coverage
  • Built-in Protocol checks
  • Extensive error injection

Key Features

  • I2C v3.0 supported
  • Standard-mode, fast-mode, fast-mode plus, and high-speed mode
  • Both 7-bit and 10-bit addressing
  • Includes master agent, slave agent, monitor and checker
  • Slave agent can be configured as a generic slave or as an EEPROM slave
  • Glitch insertion and rejection
  • Configurable clock stretching
  • Multiple masters and slaves configuration supported
  • Arbitration and clock synchronization
  • General Call, Start Byte, Bus Clear Configurability for NACK response generation
  • Mixed Speed Mode