VC Verification IP for SDIO
Synopsys VC Verification IP for SDIO provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of SDIO based designs.
Protocol Features
- SDIO specification 4.0
- Host and card model
- All data widths (1 and 4 bit)
- All transfer modes (single and multiple blocks)
- Byte and block mode operation
- All speed modes
- Write/Read break off
- Function unique area
- Function basic register(FBR)
- Code storage area(CSA)
- Software reset
- SDIO interrupts
- Asynchronous interrupts
- Read wait
- Suspend/Resume
