VC Verification IP for SWD

Synopsys® VC Verification IP for SWD provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of SWD based designs.

Verification IP for SWD

Highlights

  • Native SystemVerilog/UVM
  • Runs natively on all major simulators
  • Built-in protocol checks
  • Built-in verification plan and coverage
  • Verdi® Protocol Analyzer
  • Extensive error injection

Key Features

  • SWD master and slave
  • Configurable turnaround period
  • SWD master feature set
    • Programmable clock frequency of operation
    • Flexibility to perform data phase after WAIT or FAULT response
    • Command types: Debug Port Write, Debug Port Read, Access Port Write, Access Port Read, Line Reset
  • SWD slave feature set
    • ACK types: OK, WAIT, FAULT, INVALID
    • Callback support after request phase to set required ACK Type
    • Callback support after ACK phase to set the required data value for READ commands