VC Verification IP for SWD

Synopsys® VC Verification IP for SWD provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of SWD based designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

Verification IP for SWD

Highlights

  • Native SystemVerilog/UVM
  • Runs natively on all major simulators
  • Built-in protocol checks
  • Built-in verification plan and coverage
  • Verdi® Protocol Analyzer
  • Extensive error injection

Key Features

  • Supports SWD versions 5.0 & 5.2
  • SWD master and slave
  • Configurable turnaround period
  • SWD master feature set
    • Programmable clock frequency of operation
    • Flexibility to perform data phase after WAIT or FAULT response
    • Command types: Debug Port Read/Write, Access Port Read/Write, Line Reset, User Control, SWD to/from JTAG, Dormant to/from SWD, Dormant to/from JTAD
  • SWD slave feature set
    • ACK types: OK, WAIT, FAULT, INVALID
    • Callback support after request phase to set required ACK Type
    • Callback support after ACK phase to set the required data value for READ commands
    • Multi-drop feature as per v5.2