VC Verification IP for TileLink

Synopsys® Verification IP for TileLink provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of RISC-V architecture based SoCs.



  • SystemVerilog, UVM/OVM testbench
  • Built-in coverage
  • Built-in protocol checks
  • Synopsys Verdi protocol-aware debug
  • Error injection and callbacks

Key Features

  • Supports TileLink 1.8.0 and 1.8.1 specifications
  • Driver, receiver, and crossbar agents
  • TL-UL, TL-UH and TL-C conformance levels
  • All channels:
    • TL-UL support Channel A & D
    • TL-UH support Channel A & D
    • TL-C support Channel B, C & E
  • All request and response messages
  • Comprehensive same channel and cross channel delays 
  • Data widths: 32, 64, 128, 256, 512, 1024-bits
  • All burst-size up to 4KB
  • Out-of-order responses
  • User defiled FIFO mode (in-order) responses

Additional Information

Contact us to learn more about Synopsys Verification IP for TileLink and related protocol verification solutions for simulation, emulation, and prototyping.