VC Verification IP for AVSBus

Synopsys® VC Verification IP for AVSBus provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of AVSBus based designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.

Highlights

• Native SystemVerilog/UVM
• Built-in protocol checks
• Verification plan and coverage
• Verdi® Protocol Analyzer
• Extensive error injection
• Runs on all major simulators

Key Features

• Specifications supported: PMBus Part III— AVSBus Revision 1.3.1
• Agent can be configured as Master or Slave
• Automated Error Injection
• Configurable Pattern generation for Random, Directed and Error patterns
• Debug ports and Analysis Ports
• Protocol Features
    – Supports 2-wire and 3-wire mode of operation
    – Supports Slave Resynchronization
    – Configurable Clock time period
    – Clock suspension when inactive
    – Bus timeout function implemented in Slave
    – Supports all AVSBus commands
    – Supports manufacturer-specific commands
    – Supports back to back frame generation
    – Supports Status Response frame
    – Supports Interrupt generation (Slave) and handling (Master)
    – Clock stalling support in master VIP
    – Timing parameter support in VIP and checker