Verification IP for Fibre Channel

Synopsys® Verification IP (VIP) for Fibre Channel is designed to thoroughly verify Fibre Channel designs using both random and directed simulation. The Fibre Channel VIP provides full protocol functionality and includes application layers that vastly simplify testbench development. Application layers provide simple APIs to act as a SCSI initiator, SCSI target or as a User-defined application.


  • Verilog test bench with SystemVerilog/UVM wrapper
  • Runs on all major simulators
  • Built-in protocol checks
  • Extensive error injection

Key Features

  • FC layers:
    – FC-4 and FC-2 (Transport Layer)
    – FC-2 (Link Layer)
    – FC-1 (Encoder/ Decoder)
    – FC-0 (Serializer/ Deserializer)
  • Speed modes:
  • Interfaces:
    – Parallel interface with user defined data width
    – Serial interface
    – PAM4 interface
  • Transmitter Training
  • Speed Negotiation
  • Randomized error injection
  • Verbosity controlled logging
Verification IP for Fibre Channel

Other Features

  • Compliant to SCSI architecture model 4 (SAM-4)
  • Supports multi LUN addressing
  • Comprehensive suite of SVC settings that define the behavior and parameters of the commands/task management functions executed by the initiator
  • Supports several queuing attribute models
  • Host model capabilities:
    • A single initiator can communicate with multiple targets
    • Initiator can discover target information or have this step skipped   and set with appropriate target information
  • Target model capabilities:
    • Target implements a block mode device
    • Target is multiple LUN capable
    • Capable of responding to discovery commands such as INQUIRY, REPORT_LUNS, etc.

  • Corresponds to the FC-4 Mapping layer and a subset of the FC-2 Protocol layer defined in Fibre Channel
  • Raw and User Defined Frame Generator
    Frame level error detection (e.g. CRC, destination ID, etc.)
  • Port and process login
  • Extended link services stimulus/response engine
  • Frame level statistics
  • FC-FS, FC-PH compliant framing generation and checking
  • Adaptable to multiple FC-4 applications
  • SCSI over Fibre channel (FCP-3 Compliant)
  • FCP statistics
  • SAM standard SCSI interface
  • Multiple outstanding IOs/exchanges
  • Randomization of sequence behavior stressing common pitfalls in FCP

  • Processes incoming and outgoing data, a Dword at a time
  • Configurable port - Nport or Lport
  • FC-AL-2 loop port state machine
  • Port state machine compliant to FC-FS for Nport
  • Ordered set sequence validation
  • Elasticity buffer
  • FC-1
    • Compliant to FC-PH, FC-FS-2
    • Disparity checking
    • Kcode and Dcode checking
    • 8b/10b encode and decode functions
    • Controls to inject bit errors
  • Controls for Dword/primitive override
  • FC port state machine
  • Nport statistics (e.g. interframe gap, simultaneous Rx/Tx traffic detection, etc.)
  • FC-AL
    • Compliant FC-AL2 state machine
    • Configurable parameters to vary loop behavior
    • Complete loop initialization stimulus/response (LIM selection, LIFA, LIPA, LIHA, LISA, LIRP, LILP handling)
  • Lport statistics (e.g. duplex detection, loop tenancy behaviors)

• Encoder/Decoder
• 8B/10B transmission code
• 64B/66B transmission code (FC_FS4)
• 256B/257B transmission code (FC_FS4)
• Support for clause 74 16G FEC.
• Support for RS (528-514)
• Support for RS (544-514)

  • Supports serializer/de-serializer with clock recovery
  • Configurable parallel PMA interface of width of 10, 16, 20, 40 or 64 bits
  • Support for transmitter training (FC-FS-4 section 9)
  • Transmitter training support for speeds 16G/ 32G/ 64G/ 128G
  • Speed negotiation support for speeds 1/2/4/8/16/32G/64G/128G with transmitter training. (FC-FS-4 section 8)
  • Supports configurable timers

Contact the VIP Team