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- Verilog test bench with SystemVerilog/UVM wrapper
- Runs on all major simulators
- Built-in protocol checks
- Extensive error injection
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VC Verification IP for Fibre Channel
Synopsys VC VIP for Fibre Channel is designed to thoroughly verify Fibre Channel designs using both random and directed simulation. The Fibre Channel VIP provides full protocol functionality and includes application layers that vastly simplify testbench development. Application layers provide simple APIs to act as a SCSI initiator, SCSI target or as a User-defined application.
Key Features
- FC layers:
– FC-4 and FC-2 (Transport Layer)
– FC-2 (Link Layer)
– FC-1 (Encoder/ Decoder)
– FC-0 (Serializer/ Deserializer) - Speed modes:
1/2/4/8/10/16/32/64/128G - Interfaces:
– Parallel interface with user defined data width
– Serial interface
– PAM4 interface - Transmitter Training
- Speed Negotiation
- Randomized error injection
- Verbosity controlled logging