Contact Sales
ansys.com
Synopsys and Ansys power the future of innovation—connecting silicon to systems.
EDA
System
IP
SolvNetPlus
Training & Education
Architecture and Key Features
Specifications: Fibre Channel upto 128G
Key VIP Features
- Full Initiator and target models
- Scoreboard, callbacks and error injection
- Configurable pattern generation for random, directed or erroneous patterns
- Constrained-randomized parameters to aid in coverage during randomized testing
Debug and Analysis
- Waveform visibility of VIP signals
- Verbosity controlled logs
- Statistics reported at each level to help determine corner case coverage
Key Protocol Features
- Supported speeds: 1/2/4/8/16/32G/64G/128G
- Supports XAUI, L, N, and F ports
- SAM-4 Application-level exerciser for both unit and system level testing
- Supports multiple instantiations to test multi-port hosts, switches or device
- Supports port state machine compliant to FC-FS for Nport
- Supports speed negotiation (FC-FS-5)
- Supports randomized error injection
- Supports interface connectivity via Parallel interface with user defined width
- •Serial interface
Ask
i
NOTICE: You are interacting with an AI-powered chatbot that provides general information about Synopsys, including its products and services, which may be incorrect or incomplete. In the event of any conflict or discrepancy, the terms of your applicable agreements supersede any information provided by this chatbot. These chats may be accessed by Synopsys and its service providers to customize the experience and improve this tool, and your use of this chatbot is an agreement to that data processing activity.