VC Verification IP for JTAG

Synopsys® VC Verification IP for JTAG provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of JTAG based designs. VC VIP JTAG is integrated with Verdi Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of memory operations. VC VIP JTAG is written entirely in SystemVerilog to run natively in any IEEE SystemVerilog compliant simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and a sequence collection.

Verification IP for JTAG


  • SystemVerilog testbench
  • Native UVM support
  • Runs natively on all major simulators and Verification Compiler™
  • Built-in verification plan and coverage
  • Built-in Protocol checks
  • Protocol-aware debug
  • HTML based documentation

Protocol Features

  • Supports IEEE 1149.1-2013 JTAG Protocol Standard
  • Configurable instruction register
  • Configurable data register width
  • Dynamically configurable data register width
  • User defined instructions
  • User defined data registers
  • Reports current state of TAP finite state machine