Highlights
- SystemVerilog and Verilog testbench
- Native UVM/OVM support
- Runs natively on all major simulators
- Verdi Protocol-aware debug
- Verification plan and coverage
- Built-in Protocol checks
- Error injection and exceptions
- Debug port
- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Software Integrity
- Tools & Services
- Solutions
- Customer Success
- Partners
- Resources
- Blog
- Intelligent Risk Management
- AppSec Testing Orchestration
- Vulnerability Correlation & Prioritization
- DevSecOps Integrations
- Manage Business and Software Risk
- Manage software risk at the speed your business demands.
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers & Culture
< Silicon Design & Verification
Silicon Design & Verification
< Products
< Products
< Products
< Products
< Products
< Products
< Products
< Products
< Silicon Design & Verification
< Solutions
< Solutions
Cloud
Synopsys in the Cloud
< Solutions
< Solutions
< Solutions
< Solutions
< Silicon Design & Verification
< Resources
< Resources
Verification
Articles
Blogs
Datasheets
Events
News
Newsletters
Success Stories
Videos
Webinars
White Papers
< Resources
< Silicon Design & Verification
< Services
< Services
< Services
< Silicon Design & Verification
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Silicon Design & Verification
< Training
< Silicon Design & Verification
Training
Training and Education
< main menu
< Silicon IP
Silicon IP
< Products
< Products
Processor Solutions
ARC Processor IP
Embedded Vision Processor IP
Development Tools
Operating Systems
Ecosystem
ASIP Tools
< Products
Memories & Libraries
Logic Libraries
Memory Compilers
Duet Packages
HPC Design Kit
PVT Sensors
Non-Volatile Memory
< Products
< Products
Analog IP
Data Converters
< Products
< Products
< Products
< Silicon IP
< Markets
< Silicon IP
Newsletter
< Silicon IP
Customer Success
< Silicon IP
News
< Resources
< Resources
< main menu
< Software Integrity
Software Integrity
< Tools & Services
Intelligent Risk Management
AppSec Testing Orchestration
Vulnerability Correlation & Prioritization
DevSecOps Integrations
< Tools & Services
< Tools & Services
Holistic Program Development
AppSec Program Strategy
Threat & Risk Assessments
Security Training
Open Source Audits
Implementation & Deployment
< Software Integrity
< Solutions
Manage Business and Software Risk
Manage software risk at the speed your business demands.
< Solutions
< Solutions
< Solutions
< Software Integrity
< Customer Success
< Customer Success
< Customer Success
< Software Integrity
< Software Integrity
Partners
< Resources
< Resources
< Software Integrity
< Software Integrity
Blog
< main menu
Software Integrity
Software Integrity
+
Tools & Services
+
Solutions
+
Customer Success
Partners
+
Resources
Blog
< About Us
Company
< About Us
< About Us
About Us
About Us
< Investor Relations
< About Us
Investor Relations
Investor Relations
< Community
< About Us
Community
Community
< Newsroom
< About Us
Newsroom
Newsroom
< Resources
< About Us
Resources
Resources
< Careers & Culture
< About Us
Careers & Culture
Careers
< main menu
VC Verification IP for I2S
Synopsys VC Verification IP for I2S provides a comprehensive set of protocol, methodology, verification and ease-of-use features, enabling users to achieve accelerated verification closure of I2S designs. Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
Key Features
- Fully compliant with the I2S bus specification, rev. June 5, 1996
- Full and half duplex
- Configurable frame lengths for different (audio) transfer rates
- Left justified, right justified and PCM mode for audio transfer
- Support for dynamic reconfiguration.
- Mechanism to enable/disable data transmission, ws generation and clock generation
- Configurable as primary or secondary
- Data word length up to 64 bits
- Multi agent system env
- Transmitter and receiver agents can be used in standalone mode
- Glitch insertion and rejection
- Configurable clock stretching
Download