VC Verification IP for I2S

Synopsys VC Verification IP for I2S provides a comprehensive set of protocol, methodology, verification and ease-of-use features, enabling users to achieve accelerated verification closure of I2S designs. Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

I2S VC Verification IP

Highlights

  • SystemVerilog and Verilog testbench
  • Native UVM/OVM support
  • Runs natively on all major simulators
  • Verdi Protocol-aware debug
  • Verification plan and coverage
  • Built-in Protocol checks
  • Error injection and exceptions
  • Debug port

Key Features

  • Fully compliant with the I2S bus specification, rev. June 5, 1996
  • Full and half duplex
  • Configurable frame lengths for different (audio) transfer rates
  • Left justified, right justified and PCM mode for audio transfer
  • Support for dynamic reconfiguration.
  • Mechanism to enable/disable data transmission, ws generation and clock generation
  • Configurable as master or slave
  • Dataword length up to 64 bits
  • Multi agent system env
  • Transmitter and receiver agents can be used in standalone mode
  • Glitch insertion and rejection
  • Configurable clock stretching