Highlights
- SystemVerilog and Verilog testbench
- Native UVM/OVM support
- Runs natively on all major simulators
- Verdi Protocol-aware debug
- Verification plan and coverage
- Built-in Protocol checks
- Error injection and exceptions
- Debug port
Synopsys VC Verification IP for I2S provides a comprehensive set of protocol, methodology, verification and ease-of-use features, enabling users to achieve accelerated verification closure of I2S designs. Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.