VC Verification IP for UART

Synopsys VC Verification IP (VIP) for UART provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of all speeds and data widths.

UART VC Verification IP

Highlights

  • SystemVerilog and Verilog testbench
  • Native UVM support
  • Runs natively on all major simulators
  • Protocol-aware debug
  • Built-in verification plan and coverage
  • Built-in protocol checks
  • Error injection
  • HTML based documentation
  • Source code visibility

Key Features

  • Configurable Baud Rate Divisor
  • Configurable data-width with 5, 6, 7, 8 and 9-bits
  • Fractional Baud Rate Divisor
  • Supports full-duplex
  • Supports line break generation and detection
  • Provides hardware, or out-band, flow control
  • Provides software, or in-band, flow control
  • Supports 1 and 2 stop bits, parity (even, odd)
  • Provides receiver FIFO with configurable depth