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VC Verification IP for UART
Synopsys VC Verification IP (VIP) for UART provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of all speeds and data widths.
Protocol Features
- Configurable Baud Rate Divisor
- Configurable data-width with 5, 6, 7, 8 and 9-bits
- Fractional Baud Rate Divisor
- Supports full-duplex
- Supports line break generation and detection
- Provides hardware, or out-band, flow control
- Provides software, or in-band, flow control
- Supports 1 and 2 stop bits, parity (even, odd)
- Provides receiver FIFO with configurable depth