VC Verification IP for JESD204

Synopsys® VC Verification IP for JESD204 provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of JESD204 based designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native SystemVerilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.

Verification IP for JESD204


  • Native SystemVerilog/UVM
  • Runs natively on major simulators
  • Built-in protocol checks
  • Built-in verification plan and coverage
  • Verdi protocol-aware debug
  • Extensive error injection

Key Features

  • JESD204A/B specification
  • Tx and Rx Mode
  • Up to 32 lanes
  • Up to 256 converters
  • Serial/parallel interface
  • Transport and link layer test patterns
  • Lane skew insertion
  • All types of subclass 0-2
  • Lane alignment monitoring, correction and character replacement
  • Link Re-Initialization
  • Serial data rates up to 32Gbps
  • Scrambling