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EDA
System
IP
SolvNetPlus
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Architecture and Key Features
Specifications: Rev. 1.2, Look-Aside & Retransmit Extension Rev. 1.1, RSFEC Rev. 1.0
Interfaces: SERDES
DUT Types/Topology: Interlaken TX/RX
Key VIP Features
- Control to enable or disable scrambler
- Specification linked Functional coverages
- Scoreboard, callbacks and error injection
- Error handling and error reporting
- Bursts and packet-level information on an analysis port
Debug and Analysis
- Additional Debug Ports to simplify debugging
- Protocol Analyzer with in-built error checking
- Monitor generated log files
- In build protocol checking
- Verdi Native Protocol Analyzer support for debug
Key Protocol Features
- Configurable BurstMax, BurstMin, BurstShort size, Meta FrameLength, Channel ON/OFF, number of Skip control words Insertion, Reset Calendar and Lane Skew
- Automatic addition of Idle Control Word to confirm to burst short
- Up to 96 lanes with having Gear Box width of 1 bit up to 67-bit
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