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VC Verification IP for Interlaken
Synopsys® VC Verification IP for Interlaken provides a comprehensive set of protocol, methodology, verification and ease-of-use features, enabling users to achieve accelerated verification closure of Interlaken designs. Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
Highlights
- SystemVerilog, UVM/OVM testbench
- Runs natively on all major simulators
- Built-in coverage
- Built-in protocol checks
- Verdi protocol-aware debug
- Trace file for easy debug
- Error injection and callbacks
Key Features
- Compliant to Interlaken Protocol Specification Rev 1.2, Interlaken Look-Aside Protocol
- Definition Rev 1.1, Interlaken Retransmit Extension Protocol Definition Rev 1.1
- Configurable BurstMax, BurstMin, BurstShort size, Meta Frame Length, Channel ON/OFF, no. of Skip control words Insertion, Reset Calendar and Lane Skew
- Up to 96 lanes with Gear-Box width of 1 bit to 67-bit
- Up to 64K channels using Multi Use bits
- Supports both In-band and Out of band flow control