Functional Verification Datasheet Download

VC Verification IP for SMBUS

Synopsys® VC Verification IP for SMBUS provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of SMBUS designs. Synopsys VC VIP, based on its next generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences. VC VIP for SMBUS is integrated with Verdi® Protocol Analyzer, a protocol aware debug environment that gives users an easy to understand, graphical view of complex protocol traffic.

Please complete the following form then click 'continue >>' to complete the download.   Note: By registering, you acknowledge and agree to the terms of the Synopsys Privacy Policy.

Required Required Fields

Business Email:Required
First Name:Required
Last Name:Required
Job Title:Required
Postal/Zip Code:Required

(requires browser cookies to be enabled)