Verification IP for Ethernet (Up to 1.6T)

Specifications

• IEEE 802.3 dj v1.5,by,df,cb(2.5G Base-X & 5G Base-R), 802.1ae(MACSec)
• ETC 25/50G, AVB TSN, Auto-Negotiation(CL28, CL37, CL73, CL98)
• PCS Clause 40(1000 BaseT), Clause 82(40/100G PCS), Clause 96(100 Base T1), Clause 97(1000 Base T1), Clause 107(25G PCS), Clause 119(200/400G PCS), Clause 133(50G PCS)
• FEC Clause 74 (FEC), Clause 91(RS FEC), Clause 134(RS FEC:50G), Clause 108(RS FEC: 25G), LL FEC(25-50G Consortium)
• Serializer: Base–R, XAUI, KR4 (XLAUI) & CR10 (CAUI), 25GAUI, 50GAUI, 100GAUI, 200GAUI, 400GAUI, 800G AUI, 100 Base T1, 1000 BaseT1(IEEE BP & BW) Flex E(OIF-FLEXE-02.1)
• Auto-Adaptation CL72, CL93, CL94, CL136, CL162
• MDIO Interface (CL22 and CL45)
• MACSec (IEEE 802.1 AE / AEbn / AEbw / AEcg)
• Low power idles (EEE for clauses 35, 36, 46, 48, 49, 73, 74)
• Energy Efficient Ethernet (EEE)

Interfaces: 1G (SGMII), 2.5G /5G, QSGMII, USGMII, USXGMII-M, OSGMII, 400GMII/200GMII 

DUT Types/Topology: MAC to MAC, MAC+PHY(serial/parallel) to MAC+PCS (serial/parallel)

Key VIP Features

• All Ethernet speeds up to 1.6T (10/100M & 1/10/25/40/50/100/200/400/800G/1600G)
• Specification linked Functional coverages & Verification plans
• Analysis ports for Scoreboard, TLM ports, callbacks and error injection
• Emulates MAC & PHY
• Dynamic speed switching
• Custom header and payload insertion
• Ready for Back-annotation  

Debug and Analysis

• Verdi based protocol and performance analysis
• Protocol checks at each layer
• Debug ports, Transaction log, Verbosity Messages, trace files & FAQ

Key Protocol Features

• Ethernet 1.6T
  • 64/66-bit Encoding/Decoding, 256/257-bit Transcoding
  • Gray Encoding and Precoding with PAM4 Modulation
  • Events indicating key protocol signatures:
    • PCS / RS / RS FEC Link UP
    • Frame Accept /Reject, Frame Start / End etc
    • Ethernet VIP Frame Generator
  • Alignment marker Mapping and insertion/removal
  • Support for PAM4 Encoding for 400G/200G/100G/50G
  • RS(544,514) Reed-Solomon encoder/decoder
  • FEC Code words interleaving 10-bits at a time
  • Lane re-ordering & De-interleaving on Rx
  • User Defined Align Marker Characters/Timer
  • PCS Lane Reversal and Skew Insertion
  • Clock Data Recovery
  • Parallel Interfaces, User defined Lane Widths
  • Programmable Degraded SER /HI SER thresholds
  • MAC Data, Control, PPP, PTP 1588, VLAN, SVLAN, AVB (TSN), JUMBO
  • Fully Customizable L2/L3/L4/L7 packets frames
  • MII, RMII, SMII, GMII, RGMII, XGMII, XLGMII, XXVGMII, LGMII, CGMII, CDMII (400G), CCMII (200G), DCCCMII (800G) MAC
  • MAC Control Frames (Pause Frames), PFC
  • PCS Layer: TBI, XSBI, XFBI, XLSBI, CSBI, XXVSBI, LSBI, 2.5GBASE-X, 5GBASE-R, CDXBI (400G), CCXBI (200G), DCCCXBI (800G)
• Ethernet 800G
  • Independent 32 lanes of 10-bit data [800 Gigabit ten Bit Interface (DCCXBI) with 800 Gb/s speed]
  • Independent 32/16/8 lanes of Serial-bit data
  • 64/66-bit encoding/decoding, 256/257-bit transcoding, Gray encoding and precoding with PAM4 modulation
  • RS(544,514), Force loss of synchronization
  • Insert skew between lanes, Configurable Align Markers
  • Alignment marker corruption–selective nibble corruption/full AM
  • Lane reordering, Bit Muxing
  • Flexible lane Muxing (Flexibility to user-defined lanes combination)
  • Quartet Symbol-mux
  • Delay odd PCSL by one RS-FEC symbol
  • Alignment marker Mapping and insertion/removal
  • RS(544,514) Reed-Solomon encoder/decoder
  • FEC Code words interleaving 10-bits at a time
  • Lane re-ordering & De-interleaving on Rx
  • User Defined Align Marker Characters/Timer
  • Gray Encoding and Precoding with PAM4 Modulation
  • PCS Lane Reversal and Skew Insertion
  • Clock Data Recovery
  • Parallel Interfaces, User defined Lane Widths
  • Programmable Degraded SER /HI Ser thresholds etc
• Ethernet 400G
  • PHY Interfaces : [Serial /Parallel ]
    • 400GAUI-16 : 16 Lane Interface
    • 400GAUI-8/200GAUI-8 :  8 Lane Interface
    • 400GAUI-4 /200GAUI-4: 4 Lane Interface
    • 400G 2 PAM4 interface with symbol muxing (ETH_400G_SERIAL_2_LANE)
    • 200G 1 PAM4 interface with symbol muxing (ETH_200G_SERIAL_1_LANE
  • NRZ and PAM4 Test Patterns
  • Programmable RS FEC Correction
  • 64/66-bit Encoding /Decoding, 256/257 bit Transcoding
  • Alignment marker Mapping and insertion/removal
  • RS(544,514) Reed-Solomon encoder/decoder
  • FEC Code words interleaving 10-bits at a time
  • Lane re-ordering & De-interleaving on Rx
  • User Defined Align Marker Characters / Timer
  • Gray Encoding and Precoding with PAM4 Modulation
  • PCS Lane Reversal and Skew Insertion 
  • Clock Data Recovery
  • Support for Low Latency FEC
  • Parallel Interfaces, User defined Lane Widths
  • Programmable SER Interval, Timer, Threshold
  • Programmable Degraded SER Assert /De-assert Threshold

Test Suites / Groups Features

• RS FEC/Align/Block/Encoder/Decoder State Machines Transitions
• Insertion of Correctible/in Correctible RS FEC Symbols
• Corruption of Fields in Control Transcode Blocks
• PCS/FEC Lane Reordering, Skew Insertion, Assertion/De-assertion of HI SER