Test Suite Features
- Support for 10/100/1G/10G/40G/100G/400G
- Provided as source code Verilog UVM
- Test plan to track pass/fail status referenced to Ethernet specifications
- Built-in coverage mapped to test plan
Writing tests to verify protocols is time consuming, challenging and requires deep protocol and methodology expertise. Synopsys testbenches help eliminate the task of writing compliance tests for today’s complex protocols.
The Ethernet test suite is a complete self-contained and design-proven testbench that covers the UNH (University of New Hampshire) interoperability test suite and is extended to cover additional tests. It spans normal data exchange cases, error injected cases and corner case scenarios to help test Ethernet designs for a wide spectrum of scenarios. It is provided as Verilog source code to simplify integration, enable user customization and maximize reuse across projects.
| 1/10/40/100G/Backplane UNH-IOL Test Suite: |
| Clauses 4/35/46/81 (MAC) – UNH MAC_Test_Suite_v5.2 |
| Clause 31 (Flow control) – UNH flow_control_testsuite_v1.5 |
| Clause 36 (TBI) – UNH CL36_PCS_Test_Suite_v2.1 |
| Clause 37 (AN) – UNH ANEG37_Test_Suite_v1.4.4 |
| Clause 46 (XGMII) – UNH Clause_46_RS_Test_Suite_V1.2a |
| Clause 48 (XAUI) – UNH Clause_48_PCS_Test_Suite_V1.3b |
| Clause 49 (Base-R) – UNH Clause_49_PCS_Test_Suite_v1.0 |
| Clause 72 (AD) – UNH Clause_72_10GBASER-KR Startup Training Test Suite v0.25 |
| Clause 73 (AN) – UNH CL73_ANEG_Test_Suite_v1.0 |
| 25/40/50/100/400G Synopsys Internal Checklist Test Suite: |
| Clause 74 (FEC) |
| Clause 82 (40/100G/400G) |
| Clause 91 (RS FEC) |
| EEE (for clauses 35, 36, 46, 48, 49, 73, 74) |
| SGMII |
| QSGMII |
| RTBI |
| RXAUI |