VC Verification IP for LIN

Synopsys® VC Verification IP for LIN provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of LIN designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

Verification IP for LIN


  • Native SystemVerilog/ UVM
  • Source code Test Suite (optional)
  • Runs natively on all major simulators
  • Built-in protocol checks
  • Verification plan and coverage
  • Verdi protocol analyzer
  • Extensive error injection
  • Transaction summary for tracing/debug
  • Debug ports
  • Verbosity controlled messaging

Key Features

  • LIN specification v2.2A
  • Primary and secondary node configurations with configurable number of secondary nodes
  • Frame types — unconditional, event triggered, sporadic, diagnostic, reserved
  • Sleep and wake up modes
  • Configurable baud rate operations
  • Error injection and detection
  • Stimulus generator, protocol checkers and data collectors
  • Callbacks for user defined read and write