VC Verification IP for LIN

Synopsys® VC Verification IP for LIN provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of LIN designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

VC VIP for LIN is integrated with Verdi® Protocol Analyzer, a protocol aware debug environment that gives users an easy to understand, graphical view of complex protocol traffic.

Verification IP for LIN


  • Native SystemVerilog/Verilog with UVM
  • Source code testsuite (optional)
  • Runs natively on all major simulators
  • Built-in protocol checks
  • Verification plan and coverage
  • Verdi protocol analyzer
  • Extensive error injection

Key Features

  • LIN specification v2.2A
  • Master and slave node configurations with configurable number of slave nodes
  • Frame types — unconditional, event triggered, sporadic, diagnostic, reserved
  • Sleep and wake up modes
  • Configurable baud rate operations
  • Error injection and detection
  • Stimulus generator, protocol checkers and data collectors
  • Callbacks for user defined read and write