VC Verification IP for FlexRay™

Synopsys® VC Verification IP for FlexRay™ provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of FlexRay designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

VC VIP for FlexRay is integrated with Verdi® Protocol Analyzer, a protocol aware debug environment that gives users an easy to understand, graphical view of complex protocol traffic.

FlexRay VC Verification IP

Highlights

  • Native SystemVerilog/UVM test bench
  • Runs natively on major simulators
  • Built-in protocol checks
  • Verification plan and coverage
  • Extensive error injection
  • Verdi protocol-aware debug

Protocol Features

  • Host, communication controller, bus driver
  • Bit rates — 10Mbps, 5Mbps and 2.5Mbps
  • 1 or 2 communication channels
  • Message buffer configurable from 2 bytes up to 254 bytes
  • Communication cycle — Static segment, dynamic segment, symbol window, NIT (network idle time)
  • Synchronization methods —TT-D, TT-L, TT-E (Optional)
  • Frame ID, cycle counter and channel based message filtering for Tx and Rx buffers
  • Single or multi-master clock synchronization
  • Bit strobing
  • Synchronus and asynchronus frame transfer
  • Error detection and signaling
  • Scalable fault tolerance
  • Network topologies —Bus, star, hybrid (bus and star mixed)