VC Verification IP for CAN 2.0/FD/TT

Synopsys® VC Verification IP for CAN 2.0/FD/TT provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of CAN based designs.

Synopsys VC VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VC VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

Verification IP for CAN 2.0/FD/TT


  • Native SystemVerilog/UVM testbench
  • Source Code Test Suite (optional)
  • Runs on all major simulators
  • Built-in protocol checks
  • Verification plan and coverage
  • Verdi integrated protocol-aware debug
  • Error injection
  • Extensive callbacks and messaging

Key Features

  • CAN 2.0 (Part A, Part B)
  • CAN Flexible Data Rate (CAN FD)
  • Time Triggered CAN (CAN TT Level 1 & Level 2)
  • Compliant to ISO 16845 and 11898-1:2015
  • Supports all 4 frame types
  • Supports all 5 types of error insertion and detection
  • Tracks TEC/REC Error counters
  • Retransmission of corrupted messages for configurable maximum attempts
  • Test suite supports 16845 ISO/DIS, ISO 11898-1:2015, and internal checklist tests