VC Verification IP for Ethernet

Synopsys® VC Verification IP for Ethernet 10/100/1000M and 10/25/40/50/100/200/400G provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of Ethernet based designs.

Verification IP for Ethernet

Highlights

  • Native SystemVerilog/UVM
  • Source code test suite including UNH-IOL (optional)
  • Runs natively on major simulators
  • Built-in protocol checks
  • Verification plan and coverage
  • Verdi® Protocol Analyzer
  • Trace file support for debugging
  • Extensive error injection

Key Features

  • Ethernet 10/100M, 1/10/25/40/50/100/200/400G
  • IEEE 802.3-2015
  • IEEE P802.3bs (200/400G Base-R)
  • IEEE 802.3cd 100G RS-FEC (with optional FEC states), 50G Base-R, PAM4 Encoding
  • IEEE 802.3bj (40/100G Base-R, 100G Base-R RS-FEC)
  • IEEE 802.3 by and consortium 25/50G
  • AVB TSN specifications and drafts
  • IEEE802.3cb (2.5G Base-X & 5G Base-R)
  • IEEE 802.1AE (MACSec)
  • USXGMII-M, QSGMII
  • Flex Ethernet (OIF-FLEXE)
  • Energy Efficient Ethernet (EEE)
  • Auto-adaptation
  • Auto-negotiation
  • MDIO clause 22 and clause 45
  • Dynamic speed switching
  • Custom header and payload insertion
  • Debug port