Verification IP for eUSB 2 v2 and USB 2.0

Specifications: eusb2v2 rev0.9, USB 2.0

Interfaces: ​UTMI/ULPI/Serial/HSIC/EUSB2 (V1 & V2)

DUT Types/Topology

• USB 2.0 - Host, Device, PHY and  HUB
• EUSB2.0 - Repeater, Native Controller and PHY

Key VIP Features

• Specification linked Functional coverages
• Scoreboard, callbacks and error injection
• Speed modes - HS/FS/LS 

Debug and Analysis

• Verdi based protocol and performance analysis
• Protocol checks at each layer
• Debug ports and trace files

Key Protocol Features

• Protocol Layer Features
  • All transfer types (Ctrl, Bulk, intr, Iso & Split transfers)
  • High bandwidth Iso/Interrupt transfers, Interleaving transfers/Ping transfers
  • Different handshaking response  (NAK/NYET/STALL/Nohandshake(timeout))
  • Device framework transfer initiation
  • PL Exceptions and error injections in packets (CRC16/5 error/Invalid PID/NPID/packet field errors, timeout)
• Link Layer Features
  • All state machines entry/exit, Power mgmt. state entry/exit(L1/L2)
  • Vbus cut off in-between transfers & during suspend
  • Disconnect/connect during transfers & during reset, protocol reset in-between transfers
  • Fslsserialmode/Test mode support
  • OTG-SRP/HNP/ADP
• PHY Features
  • Physical Exception and error injections(invalid SYNC and EOP, Bit-stuff error, Rxerror scenarios etc…)
  • Sync/EOP length adjustment, Preamble mode support
  • Keep alive(HS/LS) support

Test Suites / Groups Features

• Host/Device/HUB/PHY/XHCI
• AHB/AXI bus interface support along with system memory and backdoor
• Multi-controller and Multi-port support
• Tailor Made for Testbench Migration from IP level to SoC level
• Includes the Application Layer