VC Verification IP for SAS

Synopsys VC Verification IP (VIP) Serial SCSI (SAS) is designed to thoroughly verify your design using both random and directed simulation.

VC VIP SAS provides full SAS functionality and includes application layers that vastly simplify testbench development. Application layers provide simple APIs to generate SAS traffic: a SCSI application layer, an STP Host Exerciser and Management application layer.

Verification IP for SAS

Highlights

  • Verilog/SystemVerilog testbench
  • Runs natively on major simulators
  • Built-in protocol checks
  • Extensive error injection

Key Features

  • Support for SAS SPL5 specification
  • All speeds up to 24G (1.5, 3, 6, 12 and 24G)
  • Acts as Initiator or Target
  • OOB sequence generation/checking
  • Full expander models, SMP port
  • Speed negotiation, training, and multiplexing at any link speed
  • SCSI Application level exerciser for both unit and system level testing
  • Optional STP support with ATA Application level exerciser
  • Scalable for multiple instantiations to test multi-port hosts or devices
  • Serdes, 10b, 20b, 40b and link layer Dword36/Packet interfaces
  • Protocol and timing check at each layer
  • Configurable pattern generation for random, directed or erroneous patterns
  • Constrained-randomized parameters to aid in coverage
  • User call-backs and hooks for directed tests
  • ASCII signals in each layer for easy debug