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Synopsys is a leading provider of electronic design automation solutions and services.

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Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs.

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VC Verification IP for SATA

Synopsys VC Verification IP (VIP) for Serial ATA (SATA) is designed to verify SATA based designs using both random and directed simulation.

Protocol Features

SATA Gen 1, 2, and 3 plus extensions
Can be used at any link speed including 6 Gb
Acts as Host or Device or Port Multiplier
Supports all SATA commands (PIO, DMA, LCQ, NCQ, Send / Receive FPDMA Queued)
Support for interrupt aggregation
OOB sequence generation and checking
Support for Serial, 10B (SAPIS), and PIPE interfaces
SERDES model capable of Receiver clock recovery
Scalable for multiple instantiations in a test bench
Configurable pattern generation for random, directed or erroneous patterns
Includes transactor interfaces for directed testing
Provides parameters for constrained random testing and accelerated coverage closure.
Support for power management modes (Partial, Slumber, DEVSLP)
Callbacks provided for directed testing