EDA
System
IP
SolvNetPlus
Training & Education
Synopsys Verification IP (VIP) for Serial ATA (SATA) is designed to verify SATA based designs using both random and directed simulation.
Protocol Features
- SATA Gen 1, 2, and 3 plus extensions
- Can be used at any link speed including 6 Gb
- Acts as Host or Device or Port Multiplier
- Supports all SATA commands (PIO, DMA, LCQ, NCQ, Send / Receive FPDMA Queued)
- Support for interrupt aggregation
- OOB sequence generation and checking
- Support for Serial, 10B (SAPIS), and PIPE interfaces
- SERDES model capable of Receiver clock recovery
- Scalable for multiple instantiations in a test bench
- Configurable pattern generation for random, directed or erroneous patterns
- Includes transactor interfaces for directed testing
- Provides parameters for constrained random testing and accelerated coverage closure.
- Support for power management modes (Partial, Slumber, DEVSLP)
- Callbacks provided for directed testing
