Explore challenges and solutions in AI chip development
Key Highlights
Ultra Ethernet, designed for scale out architectures, is an open, interoperable, high-performance protocol solution tailored for AI, supported by industry leaders across switch, networking, semiconductor, and system providers, as well as hyperscalers.
UALink, designed for scale up architectures, for high-speed communication between accelerators with large memory-sharing capabilities, backed also by significant players in the semiconductor industry.
Synopsys announced complete design and verification solutions for UEL and UAL last year- Refer to Synopsys Announces Industry's First Ultra Ethernet and UALink IP Solutions to Connect Massive AI Accelerator Clusters.
Synopsys is addressing verification requirements of high-bandwidth, low-latency interconnects with the introduction of Ultra Ethernet Verificaiton IP (VIP) and Ultra Accelerator Link VIP solutions, which provide the interfaces needed to scale today’s and tomorrow’s AI and HPC architectures.
VIP for Ultra Ethernet provides verification of design implementations based on LLR (Link Layer Retry) and CBFC (Credit Based Flow Control) specifications which can be used in SoCs and System Level Desings to accelerate verification closure for AI and HPC applications.
VIP for UAL provides verification of design implementations based on UAL_200 specification which can be used in SoCs and System Level Desings to accelerate verification closure.
With support of all 5 layers i.e. Protocol, Transaction, Data, RS and Physical layer, the Synopsys UAL solution offers:
Both these VIP’s addresses design verification complexities through following features:
Synopsys is partnering with early customers and collaborators to enhance the standard architecture for their next-generation designs, incorporating new features now available with the latest specifications.
Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer.
Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems.
More information on Synopsys UEC and UAL® VIP and Test Suites is available at http://synopsys.com/vip