Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP

Ashutosh Agrawal

Jul 18, 2025 / 3 min read

Key Highlights

  • Artificial Intelligence (AI) and HPC High Performance Computing (HPC)workloads demand high speed, high bandwidth, and low latency communication to handle massive data and parallel processing efficiently
  • Requirements to support these workloads include:
    • Scaling out (across servers) connects nodes using high-performance networking such as Ultra Ethernet
    • Scaling up (within a server) connects multiple accelerators (e.g., GPUs) using protocols such as UALink
  • Ultra Ethernet and UALink interconnects ensure fast, synchronized, and scalable AI model training and inference
  • Synopsys provides complete design, verification, validation and compliance solutions for Ultra Ethernet and UALink

Introduction

Ultra Ethernet, designed for scale out architectures, is an open, interoperable, high-performance protocol solution tailored for AI, supported by industry leaders across switch, networking, semiconductor, and system providers, as well as hyperscalers.

UALink, designed for scale up architectures, for high-speed communication between accelerators with large memory-sharing capabilities, backed also by significant players in the semiconductor industry.

Synopsys announced complete design and verification solutions for UEL and UAL last year- Refer to Synopsys Announces Industry's First Ultra Ethernet and UALink IP Solutions to Connect Massive AI Accelerator Clusters.  

Synopsys is addressing verification requirements of high-bandwidth, low-latency interconnects with the introduction of Ultra Ethernet Verificaiton IP (VIP) and Ultra Accelerator Link VIP solutions, which provide the interfaces needed to scale today’s and tomorrow’s AI and HPC architectures.

 

UAL Scale Up Network

Synopsys UEC VIP Features

VIP for Ultra Ethernet provides verification of design implementations based on LLR (Link Layer Retry) and CBFC (Credit Based Flow Control) specifications which can be used in SoCs and System Level Desings to accelerate verification closure for AI and HPC applications.

  • With support for Ultra Ethernet features such as Link-Level Retry and Credit-Based Flow Control, the Synopsys UEC VIP solution delivers comprehensive capabilities including: Flexibility to enable/disable LLR and CBFC protocol stacks separately as well in conjunction.
  • Generation of Mix traffic* along with all possible control ordered sets.  (Mix Traffic means combination of LLR Eligible and LLR In-eligible frames along with CBFC traffic)
  • Reusing existing Ethernet stack, to prevent migration and interoperability challenges.
  • Support of different Interface speeds starting from 100G upto 1.6T for both “X”MII and PHY Interfaces
  • Supporting Pause/PFC (Priority Flow Control) with LLR as well as CBFC.
  • Extensive flexibility to achieve different combinations of traffic profiles such as eligible, ineligible frames, fcs poison etc.  via transaction attributes for flexibility to model Negative Scenarios, stress test the design and to observe design behavior under different stimulus profiles.
UEC Stack

Synopsys UAL VIP Features

VIP for UAL provides verification of design implementations based on UAL_200 specification which can be used in SoCs and System Level Desings to accelerate verification closure.

With support of all 5 layers i.e. Protocol, Transaction, Data, RS and Physical layer, the Synopsys UAL solution offers:

  • Flexibility to verify individual layers.
  • Physical Layer complaint with IEEE 802.3 dj draft
  • Flexibility of using Multiple ports per VIP Instance/Pod.
  • Debug bus support at each layer for observing key protocol Indicators. 
  • Flexibility to model Negative Scenarios, stress test the design and observe design behavior under different stimulus profiles.
  • Multiple Topologies for catering different Design Types.

Both these VIP’s addresses design verification complexities through following features:

  • Native System/Verilog UVM architecture, which facilitates easy integration into simulation environments and speeds up the development of test benches.
  • Integrated verification plan, test suites, and functional coverage, to expedite the verification process and gain a competitive edge.
  • Rich configurability options and built-in protocol checks, to stay competitive in a market where protocol developments are already being adopted.
UAL Stack

Conclusion

Synopsys is partnering with early customers and collaborators to enhance the standard architecture for their next-generation designs, incorporating new features now available with the latest specifications.

Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer.

Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems. 

More information on Synopsys UEC and UAL® VIP and Test Suites is available at http://synopsys.com/vip

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