VC Verification IP for DisplayPort/eDP

Synopsys VC Verification IP for DisplayPort provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of DisplayPort, HDCP and eDP based designs.

DisplayPort VC Verification IP

Protocol Features

  • DisplayPort 1.3a specifications
  • HDCP 2.2 and 1.x specifications
  • eDP 1.4a Specifications
  • Serial interface
  • 10 bit parallel interface(Bypass PHY)
  • Main Link, 1,2,4 lanes
  • Aux Channel
  • Hot plug Detect (HPD)
  • RGB, YCbCr Colorimetric formats
  • 18,24,30,36,48 bpp
  • Audio 2~8 channels
  • Audio/Video info frames
  • EDID/DPCD registers
  • 3D Stereo Video
  • SST data
  • Clock recovery
  • Scalable architecture to support MST