Verification IP for USB 3.x

Specifications: USB 3.2/3.1/3.0/2.0

Interfaces: PIPE 5/4, Serial ​

DUT Types/Topology: Host, Device, PHY, Hub, Redriver, Retimer

Key VIP Features

• All Speed modes: SSP/SS, USB 3.2, 10Gbps for SSP/5Gbps for SS
• Specification linked Functional coverages
• Scoreboard, callbacks and error injection  

Debug and Analysis

• Protocol Analyzer with Unified Debug Environment
• Debug Ports in Waveform Dumps

Key Protocol Features

• Protocol Layer:
  • All transfer types (Ctrl, Bulk, intr, ISOC, Bulk Streaming, Pipeline ISOC, LMP)
  • Interleaving transfers/Simultaneous IN & OUT/Ping transfers
  • Different handshaking response (NRDY/ERDY/STALL)
  • Device framework transfer initiation
  • PL Exceptions and error injections in packets (CRC16/32 error/Invalid DP/HP/packet field errors etc)
• Link Layer Features
  • All state machines entry/exit, Power mgmt. state entry/exit (U1/U2/U3), Connect/Disconnect
  • Link Exceptions and Error injections (LBAD/LRTY/CRC5 etc)
  • Configurable config lane, Lane based exception for symbol set
  • Control to start packet/ link command on config or non-config lane
  • LFPS on non-config lane
• PHY Features
  • 128/132 bit encoding for SSP and 8/10 encoding for SS
  • Jitter/clock recovery/DC balancing/Block alignment & SKP OS handling/SSC
  • Dual lane support, Physical Exception and error
• Test Suites / Groups Features
  • USB 3.x Link layer Compliance, directed and constrained random tests
  • XHCI Driver support along with XHCI tests
  • AHB/AXI bus interface support along with system memory and backdoor
  • Multi-controller and Multi-port support
  • Simple Sequence creation and debugging
  • Plug‑and‑Play Framework for IP‑Level Verification and Testbench Migration from IP to SoC Includes the application layer & Capability to add Custom sequences