VC Verification IP Test Suites

VC Verification IP Test Suites

Writing tests to verify today’s complex SoC bus and interface protocols is extremely time-consuming and challenging, requiring deep protocol and methodology expertise.

Synopsys Test Suites are a set of directed tests providing tests for items in the specification to help accelerate testbench development and closure. Test suites are used together with the VIP.  

Verification IP for Test Suites

Synopsys Test Suites include UVM tests along with a UVM environment that help verify the IP/Subsystem covering the entire protocol specification. The test suite is delivered as source code with no encryption after installation. Licensed users can run parallel simulations. The tests are targeted to provide very high functional coverage, as close as possible to 100%, covering all protocol features, corner cases, error scenarios, stress tests, etc. The number of tests can be in the thousands for bigger protocols like PCIe, USB, Ethernet or few hundred for simpler protocols.

Since test suites are source code, the user has full control on all sequences and tests to modify, enhance or build new tests. Customers of Synopsys VIP Test Suites have been able to save months of testbench development, debug time, time to 1st test pass, start verification with limited protocol knowledge.

Test Suite Highlights

  • Readymade environment components available for faster DUT integration
  • Fully Open Source System Verilog UVM
    • Code is extensible for developing new tests
  • Integrates with the Synopsys Integrated IP Core or 3rd party Cores
  • Tests for all protocol layers & all possible verification topologies
  • Test Suite provides Callbacks to alter the behavior of tests
  • Leverages VIP built-in functional coverage and protocol checks
  • Verification plan referenced to specification
  • Supports all major simulators