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VC Verification IP Test Suites
Writing tests to verify today’s complex SoC bus and interface protocols is extremely time-consuming and challenging, requiring deep protocol and methodology expertise.
Synopsys test suites are available for selected protocols. Written natively in SystemVerilog UVM, they are provided as source code to reduce or eliminate the challenge of developing a verification environment and tests for protocol-compliance verification.
Synopsys test suites are complete, self-contained and design-proven testbenches. Access to source code enables users to easily customize or extend the environments to include unique application-specific tests or corner-case scenarios.
Test Suite Highlights
- Source-code
- SystemVerilog UVM
- Directed compliance tests
- Tests for all protocol layers
- SystemVerilog UVM coverage
- Verification plan referenced to specification
- Extensive protocol checks
- Coverage reports on checks
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