VC Verification IP for UniPro

Synopsys VC Verification IP for MIPI UniPro provides a comprehensive set of protocol, methodology, and verification features, enabling users to achieve accelerated verification closure of MIPI UniPro links operating in high speed and low speed modes.

VC VIP is based on next generation architecture and implemented in native SystemVerilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.

Verification IP for UFS


  • Native SystemVerilog/UVM
  • Runs on all major simulators
  • Verdi® Protocol Analyzer
  • Verification plan and coverage
  • Built-in Protocol checks
  • Optional UVM source code Test Suite (EA)

Protocol Features

  • MIPI UniPro 2.0(EA), 1.8, 1.6, 1.4
  • MIPI M-PHY 5.0(EA), 4.1, 4.0, 3.0
  • Debug port UniPro PA layer
    • Active devices: Rx debug port
    • Passive devices: Both Tx and Rx debug ports
  • Automated Lane distribution and merging of data/PACP frames
  • Lane to lane skew in both transmit and receive direction
  • Preempted frame transmission and reception
  • Automatic skip symbol insertion when enabled
  • Start VIP at various state of DME at start of simulation
  • Accelerated link startup where timers are scaled down beyond spec defined values