VC Verification IP for UniPro

Synopsys® VC Verification IP for the MIPI Alliance UniPro protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on UniPro-based designs. VC VIP for UniPro is integrated with Verdi Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand view of protocol traffic. VC VIP for UniPro is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests. VC VIP for UniPro includes support for the MIPI Alliance M-PHY protocol.

UniPro VC Verification IP

Protocol Features

  • Supports MIPI Alliance UniPro Version 1.6
  • Supports M-PHY version 3.0
  • PHY Adapter Layer
  • MPHY Serial and RMMI Interface on PHY side
  • 10/20/40 bit Symbol Length on RMMI Interface
  • Lane distribution and merging for 1 to 4 lanes
  • Full Support for PA_LM_SAP and PA_SAP primitives
  • Unipro power management operating modes
  • Transmission and Reception of PA layer Test modes Supports JEDEC UFS Version 2.0
  • Frame composition and decomposition
  • Flow control, generation of flow control
  • credit information
  • Preemption, capability to receive preempted frames
  • CRC generation and verification
  • Autonomous acknowledgment of all unacknowledged frames