Floating Point Options for ARC Cores

Power- and Area-Efficient Floating Point Unit for DesignWare ARC Processors
The DesignWare® ARC® Floating Point Unit (FPU) options for ARC EM, ARC HS, ARC VPX, and ARC EV processors adds performance-efficient single and double-precision hardware acceleration to enable floating point math acceleration. There are four versions of FPU:

  • ARC FPU for EM – Supports ARC EM4, EM6, EM5D, EM7D, EM9D and E11D processors
  • The ARC FPU for the EM processor family has full single-precision (SP) hardware support with double-precision (DP) acceleration extensions that speed up some of the more common double-precision operations and is designed specifically to be compact in area and power to match the requirements for applications the ARC EM processors target.

  • ARC FPU for ARC HS – Supports the ARC HS3x and HS4x processors
  • The ARC FPU for the HS processor family also has full single-precision hardware support but differentiates itself with more comprehensive double-precision support in the form of a much richer set of DP instructions, with full 64-bit data paths to and from HS core registers. All of the SP instructions in this FPU feature DP equivalents along with full DP to SP conversions. The HS FPU is also tailored to suit the 10-stage pipeline and high-performance nature of the ARC HS processor cores.

Both of these FPUs are supported by the ARC MetaWare C/C++ Compiler and, when used together, both of these ARC FPUs comply with the IEEE-754-2008 Standard for Binary Floating Point Arithmetic.

  • ARC VPX DSP family – Integrated within the VPX DSP processors
  • The ARC VPX VLIW/SIMD family of DSPs have multiple advanced floating point computation engines as part of the native architecture. There are two vector floating point engines, supporting half- and single-precision computation. There is also a linear algebra, math vector floating point engine, making the processor suitable for computation intensive applications such as automotive powertrain, engine management, and sensor fusion.

    The ARC VPX5 has a total of three parallel floating-point processing vector pipelines, including two optional IEEE-754 compliant vector floating point units that supports both full (32-bit) and half (16-bit) floating point operations. The VPX5 also has the option to add a dedicated vector floating point pipe, supporting an extensive set of math functions including: div, √x, 1/√x, sin(x), cos(x), log_2 (x), 2^x, e^x, atan2(x).

  • ARC VFPU (VFPU) for ARC EV – Supports the ARC EV6x processors
  • The vector FPU (VFPU) can be integrated into the EV6x embedded vision processor's vector DSP core. The VFPU is IEEE 754-compliant for ADAS applications, self-driving vehicles, powertrain, and automotive ADAS sensor fusion (linear algebra). Combined with the ARC MetaWare EV Development Toolkit, the VFPU offers performance levels of up to 328 Gigaflops for single precision operations and 655 Gigaflops for half precision operations.

Silicon-Efficient Floating Point Extensions for ARC Processors

Synopsys' ARC® FPX Floating Point Extensions add high-performance single- and double-precision math instructions to the ARC 600 and ARC 700 processor families. ARC FPX dramatically accelerates computations where data sets have a large dynamic range and when high precision is required.

When used with the ARC MetaWare compiler, DesignWare ARC FPX complies with the IEEE-754 Standard for Binary Floating Point Arithmetic. DesignWare ARC cores with DesignWare ARC FPX provide an ideal solution for system-on-chips (SoCs) that perform graphics and image processing, complex computations or control algorithms, especially where power and area budgets are constrained.

DesignWare ARC Floating Point Extensions Datasheet
DesignWare ARC Floating Point Unit for ARC EM Processors Datasheet
DesignWare ARC Floating Point Unit for ARC HS Processors Datasheet

 

Highlights
Features
Products
Downloads and Documentation
  • Very small die area and power
    • ARC FPU and FPX are both implemented using the APEX extensibility feature of the DesignWare ARC processor architectures
    • In contrast to the very large floating point co-processors required by competitive cores, ARC FPU, VFPU, and FPX instructions are integrated into the ARC cores themselves at build time
    • Synopsys' approach achieves similar floating point performance to a co-processor, but with much smaller die area and power
  • Flexible configuration options
    • SoC designers using ARC FPU can specify single precision extensions, double precision or both, as required in their application
    • SoC designers using ARC VFPU can specify half precision, single precision, or both single and double precision, as required in their application
  • Compiler math library optimizes performance
    • The ARC MetaWare compiler takes full advantage of the DesignWare ARC FPX and FPU instructions to accelerate transcendental and other functions specified in IEEE-754
    • The ARC MetaWare EV OpenCL C compiler takes full advantage of the DesignWare ARC VFPU instructions to accelerate transcendental and other functions specified in IEEE-754
  • FPU (ARC EM Family)
    • IEEE 754-2008 compliant
    • Full hardware single-precision support with double-precision acceleration
    • Full hardware single-precision (SP) and double-precision (DP) support (FPU for HS only)
    • Support for float-to-integer and integer-to-float conversion
    • Full support for SP to DP conversion (FPU for HS only)
    • Full 64-bit data paths to and from core registers (FPU for HS only)
    • Full clock-gating support for power efficiency
    • Power save features on all data paths and intermediate registers
    • Optional divide and square root support
    • Optional fused multiply/add and multiply/subtract
    • Single-cycle multiplier with two-cycle multiply option for higher frequency operation
    • Fewer than 14K gates in a single-precision, area-optimized configuration
    • Peak performance 1.0 Mflops / MHz
  • VFPU (ARC EV Family)
    • IEEE-754 compliant
    • Configurable – 1, or 2 or 3 Vector FPU pipes per core
    • Up to 512 GFLOPS (16 bit FP multiply-add, 4 cores @ 1GHz). Alternatively, VFPUs are coupled with VLIW slotting that allows all three units to execute in parallel, providing up to 200GFLOPS/second with dedicated parallel execution of algebra math functions at 12.5GFLOPS/second
    • Support both single (32-bit) and half (16-bit) floating point precision
    • ISA: multiply-add/sub, compare, min/max, reductions, convert, property
    • Supports 4-way SIMD vector math (Division, SQRT, 1/SQRT, log2(x), 2^x, Sine, Cosine, Arctan)
  • FPX (ARC 600 and ARC 700 Families)
    • Single Precision
      • MUL, ADD, SUB implemented directly in hardware
      • 3 CPU cycles latency per instruction, pipelined
      • 13 – 23x faster than an optimized software library
      • Approx. 10 - 20K gates
    • Double Precision
      • 5 CPU cycles per ADD or SUB instruction, 7 CPU cycles per MUL instruction
      • 9X - 19X faster than optimized software library
      • Peak performance: 200 Kflops / MHz
      • Approx. 25K - 30K gates
    • ARC MetaWare Math Library for FPU and FPX
      • Optimized for DesignWare ARC FPX and FPU hardware
      • Provides additional arithmetic and transcendental functions
      • Complies with IEEE-754
      • Allows re-linking of existing object files
IEEE754 compliant single and/or double precision floating point unit for ARC EM processor cores.STARs Subscribe
ARC FPX, optional Floating Point Unit, with single precision, double precision or bothSTARs Subscribe
High performance vector floating point unit option for EV6x Embedded Vision Processor familySTARs Subscribe

Description: ARC FPX, optional Floating Point Unit, with single precision, double precision or both
Name: dwc_arc_fpx
Version: 2.2.5
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: arc_ARC_FPX
Product Code: 8032-0
  
Description: High performance vector floating point unit option for EV6x Embedded Vision Processor family
Name: dwc_ev6x_vector_fpu_option
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
  
Description: IEEE754 compliant single and/or double precision floating point unit for ARC EM processor cores.
Name: dwc_arc_fpu
Version: 5.01a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: arc_em_processor
Product Code: A630-0