DesignWare ARC EM Processor Family

Unrivaled Performance Efficiency for Your Embedded Application

The DesignWare® ARC® EM Family of embedded processors is based on the scalable ARCv2 Instruction Set Architecture (ISA) and is optimized for energy and performance efficiency (DMIPS/mW and DMIPS/mm2). The ARC EM family includes the EM4 (cacheless) and EM6 (instruction and data caches) processor cores, designed for use in power and area-sensitive embedded applications. They offer industry-leading performance efficiency of up to 1.81 DMIPS/MHz, with minimal area and power consumption.

The ARC EM DSP family, which includes the ARC EM5D, EM7D, EM9D and EM11D processors, are specifically designed for ultra low-power embedded DSP applications. The EM DSP processors are based on the enhanced ARCv2DSP ISA, which adds over 100 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The processors feature a power-efficient unified 32x32 MUL/MAC unit, support for fixed point DSP vector and single instruction multiple data (SIMD) operations. The new ISA includes support for the following classes of DSP instructions and operations: basic saturating arithmetic, vector unpacking, accumulators, as well as a broad selection of MAC operations.

ARC EM Safety Island IP is a family of dual-core lockstep processors that simplifies development of safety-critical applications and accelerates ISO 26262 certification of automotive system-on-chips (SoCs). The family includes ASIL D Ready certified ARC EM4SI and EM5DSI processors that integrate a self-checking safety monitor as well as hardware safety features such as error correcting code (ECC) and a programmable watchdog timer to help detect system failures and runtime faults. The ARC EM Safety Islands are supported by comprehensive safety documentation, including failure modes, effects and diagnostic analysis (FMEDA) reports that facilitate chip- and system-level ISO 26262 ASIL D compliance.

All of the EM Processors are highly-configurable and extensible, enabling designers to implement each core with the optimum combination of performance, code density, area and power consumption for the specific task or application. In addition, ARC Processor EXtension (APEX) technology offers designers the ability to create user-defined instructions, enabling the integration of custom hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required.

The EM Family is supported by a robust ecosystem of software and hardware development tools, including an easy to use and low-cost ARC EM Starter Kit for early software development, the MQX real-time operating system (RTOS), and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC Open Software Platform.

PPA Efficiency

The ARC Advantage: Maximum Performance With Minimum Area and Power

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.

ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.

Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

Configurability

The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA

ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for

  • Instruction, program counter and loop counter widths
  • Register file size
  • Timers, reset and interrupts
  • Byte ordering
  • Memory type, size, partitioning, base address
  • Power management, clock gating
  • Ports and bus protocol
  • Multipliers, dividers and other hardware features
  • Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
  • Adding/removing instructions

Extensibility

The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption

ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:

  • User-defined instructions
  • User-supplied hardware (e.g., Verilog RTL)
  • Core registers
  • Auxiliary registers
  • Condition & status codes
  • Memory mapped blocks and closely coupled peripherals

ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings. 

The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.

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