The Synopsys ARConnect option for ARC® EM processors facilitates multicore implementations with configurable hardware for inter-core message passing, interrupt handling, semaphores and debug assistance and enhances the ability of a system to run parallel applications or pipeline stream applications.
Also included with ARConnect is a power domain management (PDM) unit and a power management Unit (PMU) to help control system power consumption. ARConnect is highly configurable and allows for each EM core to have different configurations and run at different frequencies.
Simple integration tests for ARConnect are included with the IP library and it is supported by MQX RTOS.
ARC microDMA Controller for Synopsys ARC EM Processors Datasheet
Downloads and Documentation
- Tightly coupled to the EM core interfaces for low latency, energy efficient DMA transfers
- 1 to 16 independent programmable DMA channels (configurable)
- User-programmable prioritization scheme for all channels
- Concurrent operation with the CPU
- Software and hardware triggered DMA transfers
- Two addressing modes
- Up to 5 data transfer modes (configurable down to 1)
- Internal and external interrupt support
- Configurable hardware option for efficient inter-core communications such as message passing and interrupt handling
- Enhances system ability to run parallel applications or pipeline stream applications
- Power Domain Management Unit and Power Management Unit help reduce system power consumption for a multicore system
- 64-bit Global Free-Running Counter (GFRC) for central timing reference of multiple cores running under different clock domains
- Inter-core debug unit allows selective halt and restart of any combination of cores simultaneously
|ARConnect helps customers create multi-core implementations of the ARC EM Processor Cores
|The uDMA controller for EM Processors is a programmable, small and low power memory access controller