The ASIL B, C and D compliant Synopsys ARC® VPXxFS DSP IP is a family of VLIW/SIMD processors enabling automotive system-on-chip (SoC) designers to accelerate advanced driver assistance systems (ADAS), RADAR and LiDAR sensor processing application development and ISO26262 certification for systems using digital signal processing.
The VPXxFS Family supports multiple vector lengths and core configurations:
- 128-bit vector word – VPX2FS (single core), VPX2FSx2 (dual core)
- 256-bit vector word – VPX3FS (single core), VPX3FSx2 (dual core)
- 12-bit vector word – VPX5FS (single core), VPX5FSx2 (dual core), VPX5FSx4 (quad core)
The VPXxFS Family comes with integrated hardware safety features such as ECC protection for memories and interfaces, safety monitors and lockstep mechanisms that achieve the most stringent levels of ISO 26262 functional safety compliance. To provide greater flexibility to automotive design teams, and address evolving requirements, the VPXxFS offers a “hybrid” option that enables users to select required safety levels up to ASIL-D in software, post silicon.
To speed application software development, the VPXxFS Family is supported by Synopsys’ ARC MetaWare tools, which provide a comprehensive and vector-length agnostic software programming environment that enables code portability among all members of the VPXxFS family. The tool suite includes a safety-certified optimizing C/C++ vector compiler, debugger, instruction set simulator, as well as vector-based DSP, machine learning inference and linear algebra libraries.
Synopsys ARC VPXxFS DSP Processor Block Diagram
Synopsys ARC VPX FS Datasheet
Downloads and Documentation
- Integrated hardware safety features with minimal area and power impact for full ASIL B, C, or D compliance (systematic and random)
- Four-way VLIW architecture combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector lengths
- 8, 16, and 32-bit integer SIMD engines
- IEEE 754-compliant vector floating point unit option offers single-precision or half precision operations and advanced math functions
- Dual vector floating point SIMD pipes
- Hardware acceleration for linear and non-linear math functions
- Single- and multicore-configured offerings
- AES encryption option protects valuable data such as sensor data
- ARC MetaWare tools including a safety certified auto-vectorizing C/C++ compiler, debugger, simulator, vector DSP and vector linear algebra libraries, and neural network SDK
|512-bit Vector DSP IP, Single Core with Functional Safety||STARs
|512-bit Vector DSP IP, Dual Core with Functional Safety||STARs
|512-bit Vector DSP IP, Quad Core with Functional Safety||STARs