It redefines conventional EDA tool boundaries across synthesis, place-and-route and signoff, sharing engines across the industry’s premier digital design products, and a unique, single data model for both logical and physical representation. Fusion Technology enables one DNA backbone across the Synopsys Design Platform that includes IC Compiler™ II, Design Compiler® Graphical, PrimeTime®, StarRC™, IC Validator, DFTMAX™, TetraMAX® II, and Formality® tools. It provides Design Fusion, ECO Fusion, Signoff Fusion, and Test Fusion, resulting in the most predictable RTL-to-GDSII flow with the fewest iterations, as well as unsurpassed design frequency, power, and area.
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Fusion Technology
Best-in-class optimization +
Industry-golden signoff
Fusion Technology transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff analysis, enabling designers to accelerate the delivery of their next-generation designs with the industry-best full-flow quality-of-results (QoR) and the fastest time-to-results (TTR).
"We believe Synopsys’ Fusion Technology is a game-changing innovation in the semiconductor industry, and it will certainly help Samsung Foundry, as well as our customers, to bring innovative products to market more quickly."
-Jaehong Park, senior vice president, ASIC & IP Team at Samsung Electronics
Synopsys Vision for a New Wave of Chip Design
The Semiconductor Industry is at the cusp of a new wave of chip design, accelerated by new market drivers such as automotive, artificial intelligence (AI), internet of things (IoT), 5G wireless and virtual/augmented reality (VR/AR).
Synopsys Design Platform
The Fusion of Best-in-Class Optimization and Industry-golden Signoff Tools