Advanced Fusion Technology

Advanced Fusion Technology redefines conventional EDA tool boundaries across synthesis, place-and-route, and signoff, sharing integrated engines across the industry’s premier digital design products. It enables designers to accelerate the delivery of their next-generation designs with the industry-best quality-of-results (QoR) and the fastest time-to-results (TTR).

Achieve Optimal PPA Results, Faster

Advanced Fusion technology brings synthesis optimization technology into place-and-route, and vice versa to enable better convergence and QoR. Logic restructuring provides the ability for fast area, timing, power or congestion-based re-synthesis in IC Compiler II. Coupled with RedHawk Analysis Fusion, the industry's best power-integrity-driven fixing is now available.

Design Fusion brings synthesis optimization technology into place-and-route, and vice versa to enable better convergence and QoR. Logic restructuring provides the ability for fast area, timing, power or congestion-based re-synthesis in IC Compiler II. Coupled with RedHawk Analysis Fusion, the industry-s best power-integrity-driven fixing is now available.
Signoff Fusion drives faster signoff closure by bringing PrimeTime static timing analysis, StarRC extraction, PrimePower, and RedHawk Analysis Fusion golden-signoff analysis natively inside IC Compiler II, improving flow predictability. Using PrimeTime’s golden-signoff backbone eliminates the need for excessive design margin and over-constraining for both optimization and signoff enabling perfect correlation, reduced pessimism, and superior QoR for both optimization and signoff
ECO Fusion builds on the fused signoff capabilities by reducing the need for excessive ECO iterations by allowing rapid design changes during the physical implementation phase with IC Compiler II, resulting in faster timing convergence and reducing the design cycle by up to 30%.
Test Fusion is the combination of design-for-test (DFT) RTL analysis and DFT synthesis integrated into implementation, enabling best QoR while reducing silicon test costs and turnaround time.