Considering the growing prevalence of compute-intensive applications like AI and machine learning, connected cars, and advanced robotics, it’s no wonder that memory designs have had to evolve dramatically to keep pace. As with CPUs and GPUs, memory devices too are growing larger and more complex. Multi-die configurations like multi-chip modules (MCMs) and 2.5D/3D structures are becoming more popular, providing a way to scale performance and capacity while maintaining a small footprint. High-bandwidth memory (HBM), for instance, consists of 3D stacked DRAM dies that deliver the high bandwidth, low power, and form factor ideal for applications such as networking, AI accelerators, and high-performance computing.
These new memory chip architectures present tough challenges for design, analysis, and packaging. When designing advanced HBM or 3D NAND flash chips, for example, teams must consider the complete memory array, including the interconnections between the dies and the power distribution network (PDN) to both optimize for PPA and ensure silicon reliability.
Traditional memory design and verification flows aren’t sufficient for these advanced memory devices. The excessive turnaround times of simulating large memory arrays slows time to market. Additional delays are triggered by any manual iterative loops required to resolve design issues discovered late in the process.
Employing digitization techniques in memory design can shift the process left for faster turnaround time.