NoC Design and Platform Integration for Early Benchmarking of Automotive Processor SoCs

In this presentation ST addresses their flow of architectural exploration of StellarApp SoC using Synopsys Platform Architect tool and Designware LPDDR5 model.

Validation of automotive SoCs using valid benchmark is must to guarantee all performance and design parameters are met and this could not be possible without usage of Synopsys Platform Architect tool:

1) To assemble models with different level of abstraction and from 3rd parities (ARM and Arteris )

2) Easy configuration and sweeping their parameters in different round of fast simulation

3) Effective analysis from both HW and SW point of view and 4) finally accurate model of Synopsys DW_LPDDR5 which helped us extremely fast and effective to validate our SoC with different benchmark